Integrated circuit package connected to a data transmission medium
AssigneeInternational Business Machines Corporation
InventorsHarry Barowski, Thomas Brunschwiler, Roger F. Dangel, Hubert Harrer, Andreas Huber, Norbert M. Meier, Bruno Michel, Tim Niggemeier, Stephan Paredes, Jochen Supper, Jonas R. Weiss
Life of this patent
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Abstract
An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n≧1 and N≧2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.
Claims14
An integrated circuit coupling device comprising:
- an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack, wherein each N integrated circuit layer is formed in a diced chip, with each chip being laminated so as to form the 3D stack, and wherein the stack is polished at both sides to expose bus signals of each layer;
- and
- a data transmission medium with n data transmission layers (l1-ln), wherein n≧1 and N≧2,
- and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers via electrical contacts at edges of the layers, the edges being perpendicular to a stacking direction of the 3D stack.
A method of fabrication of an integrated circuit coupling device, the method comprising:
- arranging at least a first integrated circuit layer and a second integrated circuit layer as a 3D stack in an integrated circuit package and processing electrical contacts at ends of the first integrated circuit layer and the second integrated circuit layer to enable electrical connection of the first integrated circuit layer and the second integrated circuit layer to one or more data transmission layers of a data transmission medium, wherein the first and second integrated circuit layers are electrically connectable to the one or more data transmission layers via electrical contacts at edges of the layers, the edges being perpendicular to a stacking direction of the 3D stack, and wherein the first integrated circuit layer and the second integrated circuit layer are each formed in a diced chip, with each chip being laminated so as to form the 3D stack, and wherein the stack is polished at both sides to expose bus signals of each layer.
Dependencies are inferred from the claim text.