Method and system of classifying defects on a wafer

A method of classifying defects on a wafer, comprising:

• receiving a plurality of images and a plurality of additional images acquired by a charged particle beam, wherein said images respectively correspond to a plurality of chips having similar feature on an examined wafer, and said additional images respectively corresponding to a plurality of similar chips;
• examining said images and said additional images, such that at least a defective image and at least a defect-free additional image are found, wherein said defective image includes at least one defect feature corresponding a defect on a said chip;
• translating said defect-free image into a simulated layout that corresponds to a real layout of said chips, wherein said defect-free image is formed from a plurality of pixels and has at least a pattern, and at least two of said pixels located on an edge of said pattern are connected, so as to form said simulated layout;
• and
• comparing said defective image with said simulated layout to classify said defect on said chip, wherein the comparing step comprises mapping a location of said defect feature into a mapped location of said simulated layout such that said defect is classified according to a structure located on said mapped location, said defect is classified as a hole defect when a hole located on said mapped location, wherein said defect is classified as a line defect when said mapped location corresponds to a line between chips, and wherein said defect is classified as an omissible defect when said mapped location corresponds to neither a semiconductor structure nor a conductive structure around said semiconductor structure.

A system for classifying defects on a wafer, comprising:

• a receiving module for receiving a plurality of images acquired by a charged particle beam, wherein said images respectively correspond to a plurality of chips having similar feature on an examined wafer;
• an examining module electrically connected with said receiving module for examining said images to find at least a defect-free image and at least a defective image, wherein said defective image has at least one defect feature corresponding to a defect on a said chip;
• a translating module electrically connected with said examining module for translating said defect-free image into a simulated layout that corresponds to a real layout of said chips, wherein said defect-free image is formed from a plurality of pixels and has at least a pattern, and at least two of said pixels located on an edge of said pattern are connected, so as to form said simulated layout;
• and
• a comparing module electrically connected with said examining module and said translating module for comparing said defective image with said simulated layout to classify said defect on said chip;
• and
• wherein said defect is classified as a hole defect when a hole located on said mapped location, wherein said defect is classified as a line defect when said mapped location corresponds to a line between chips, and wherein said defect is classified as an omissible defect when said mapped location corresponds to neither a semiconductor structure nor a conductive structure around said semiconductor structure.