Implementing known scrambling relationship among multiple serial links

A circuit for implementing known scrambling relationship among multiple serial links comprising:

• a respective link interface coupled to each of the multiple serial links, each said link interface including a transmit Linear Feedback Shift Register (LFSR) for scrambling transmitted data;
• and a receive Linear Feedback Shift Register (LFSR) with each of the multiple serial links for descrambling transmitted data;
• each said transmit LFSR being initialized with a respective unique value per link instance during power-on of the multiple serial links, each said transmit LFSR starts running responsive to said respective initialized unique value per link instance, and continues running during life of the power-on;
• each said respective initialized unique value per link instance being different from one another and substantially without adding of EMI radiation of each link;
• and
• each said transmit LFSR, performing a link training sequence to initialize each of the multiple serial links, said link training sequence including conveying a current unique value per link instance to a receive LFSR, for synchronizing said transmit LFSR and said receive LFSR to begin scrambling data;
• each said respective current unique value per link instance being different from one another for each said transmit LFSR.

A multiple-path local rack interconnect system comprising:

• a plurality of interconnect chips;
• a plurality of serial links connected between each of said plurality of interconnect chips;
• each of said interconnect chips including a plurality of link interfaces for implementing known scrambling relationship among multiple serial links of said plurality of serial links,
• each said link interface being connected to a respective one of the multiple serial links, each said link interface including a transmit Linear Feedback Shift Register (LFSR) for scrambling transmitted data;
• and a receive Linear Feedback Shift Register (LFSR) for descrambling transmitted data;
• each said transmit LFSR being initialized with a respective unique value per link instance during power-on of the multiple serial links, each said transmit LFSR starts running responsive to said respective initialized unique value per link instance, and continues running during life of the power-on;
• each said respective initialized unique value per link instance being different from one another and substantially without adding of EMI radiation of each link;
• and
• each said transmit LFSR performing a link training sequence to initialize each of the multiple serial links, said link training sequence including each said transmit LFSR conveying a respective current unique value per link instance to a receive LFSR for synchronizing said transmit LFSR and said receive LFSR to begin scrambling data;
• each said respective current unique value per link instance being different from one another for each said transmit LFSR.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing known scrambling relationship among multiple serial links, said circuit comprising:
• a respective link interface coupled to each of the multiple serial links, each said link interface including a transmit Linear Feedback Shift Register (LFSR) for scrambling transmitted data;
• and a receive Linear Feedback Shift Register (LFSR) with each of the multiple serial links for descrambling transmitted data;
• each said transmit LFSR being initialized with a respective unique value per link instance during power-on of the multiple serial links, each said transmit LFSR starts running responsive to said respective initialized unique value per link instance, and continues running during life of the power-on;
• each said respective initialized unique value per link instance being different from one another and substantially without adding of EMI radiation of each link;
• and
• each said transmit LFSR performing a link training sequence to initialize each of the multiple serial links, said link training sequence including each said transmit LFSR, conveying a respective current unique value per link instance to a receive LFSR, for synchronizing said transmit LFSR and said receive LFSR to begin scrambling data;
• each said respective current unique value per link instance being different from one another for each said transmit LFSR, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.