Digital phase locked loop circuitry and methods
AssigneeAltera Corporation
InventorsRamanand Venkata, Chong H. Lee
Life of this patent
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Abstract
Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
Claims20
Apparatus for converting parallel data to serial data, the apparatus comprising:
- first serializer circuitry operable to:
- receive, at a first clock rate, the parallel data;
- and
- output, at a second clock rate larger than the first clock rate, each bit of the parallel data, one bit after another in succession;
- and
- second serializer circuitry operable to:
- receive, in parallel, signals from a number of parallel leads, wherein each bit that is output by the first serializer is replicated onto each of the number of parallel leads, and wherein the number is based on a ratio of the first clock rate and the second clock rate;
- and
- output each of the signals received from the number of parallel leads, one signal after another, on a serial output lead.
A method for converting parallel data to serial data, the method comprising:
- receiving, at a first clock rate, a first set of parallel data;
- generating, at a second clock rate, a first set of serial data, the first set of serial data comprising each bit of the first set of parallel data arranged one bit after another in succession;
- and
- generating a second set of serial data, the second set of serial data comprising each bit of a second set of parallel data arranged one bit after another in succession, wherein the second set of parallel data comprises a number of instances, arranged in parallel, of each successive bit of the first set of serial data, and wherein the number is based on a ratio of the first clock rate and the second clock rate.
Apparatus for converting parallel data to serial data, the apparatus comprising:
- first serializer circuitry operable to:
- receive, at a first clock rate, a first set of parallel data;
- and
- generate, at a second clock rate larger than the first clock rate, a first set of serial data, the first set of serial data comprising each bit of the first set of parallel data arranged one bit after another in succession;
- and
- second serializer circuitry operable to generate a second set of serial data, the second set of serial data comprising each bit of a second set of parallel data arranged one bit after another in succession, wherein the second set of parallel data comprises a number of instances, arranged in parallel, of each successive bit of the first set of serial data, and wherein the number is based on a ratio of the first clock rate and the second clock rate.
Dependencies are inferred from the claim text.