Receiver with dual clock recovery circuits

A method of generating clock signals in a receiver comprising the steps of:

• generating, using a first clock and data recovery circuit, a first clock signal phase-aligned with transitions temporally after a data eye in data signals applied to an input of the receiver;
• generating, by the first clock and data recovery circuit, a first phase value indicating a phase difference between the first clock signal and a reference clock signal;
• generating, using a second clock and data recovery circuit, a second clock signal phase-aligned with transitions temporally before the data eye in the data signals;
• generating, by the second clock and data recovery circuit, a second phase value indicating a phase difference between the second clock signal and the reference clock signal;
• calculating an average of the first phase value and the second phase value to form an average phase value;
• generating a data sampling clock signal phase shifted from the reference clock signal by an amount determined by the average phase value;
• and
• slicing the data signals using a slicer clocked by the data sampling clock.

A receiver having:

• a data slicer having an output, a signal input coupled to an input of the receiver, and a clock input;
• and
• a clock generator coupled to the input of the receiver;
• wherein the clock generator comprises:
• a first slicer having an output, a signal input coupled to the input of the receiver, and a clock input;
• a second slicer having an output, a signal input coupled to the input of the receiver, and a clock input;
• a first clock and data recovery circuit coupled to the output of the first slicer and configured to generate a first phase value at an output and having a lock output for indicating that the first clock and data recovery circuit is phase-locked onto data transitions in input signals applied to the receiver;
• a second clock and data recovery circuit coupled to the output of the second slicer configured to generate a second phase value at an output and having a lock output for indicating that the second clock and data recovery circuit is phase-locked onto data transitions in input signals applied to the receiver;
• a phase averaging circuit configured to compute an average of the first phase value and the second phase value and generate an average phase value at an output;
• a multiplexer having a control input coupled to the lock outputs of the first and second clock and data recovery circuits, a first input coupled to the output of the phase averaging circuit, a second input, and an output coupled to the of the third phase shifter;
• an adder having one input coupled to the output of the first clock and data recovery circuit, a second input configured to receive a value representing a phase shift of approximately 180°, and an output coupled to the second input of the multiplexer;
• a master clock configured to generate a master clock signal;
• a first phase shifter configured to receive the master clock signal and generate a first transition sampling clock from the master clock signal and phase shifted therefrom determined by the first phase value;
• a second phase shifter configured to receive the master clock signal and generate a second transition sampling clock from the master clock signal and phase shifted therefrom determined by the second phase value;
• a third phase shifter configured to receive the master clock signal and generate a data sampling clock from the master clock signal and phase shifted therefrom determined by the average phase value;
• wherein the clock input of the data slicer is adapted to receive the data sampling clock, and the first clock and data recovery circuit is adapted to lock onto transitions temporally before the data eye and the second clock and data recovery circuit is adapted to lock onto transitions temporally after the data eye, and the phase of the data sampling clock from the third phase shifter is determined by either i) the average phase value when both clock and data recovery circuits are in phase-lock, or ii) the offset first phase value from the adder if either clock and data recovery circuit is not in phase-lock.