US 8,804,888 B2 · Wide band clock data recovery

Abstract

The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Claims11

Dependent claims

A clock data recovery circuit comprising:

a phase locked loop unit for generating a clock signal based on a first reference data signal;
a delay locked loop unit for receiving the clock signal from the phase locked loop, dividing the clock signal into a plurality of clock signals and outputting the plurality of clock signals;
and
a digital clock data recovery unit for receiving an input current signal, estimating a frequency of the input current signal, outputting a second reference data signal having the frequency to the phase locked loop unit, receiving the plurality of clock signals from the delay locked loop, aligning a phase of the input current signal based on the plurality of clock signals and outputting an aligned current signal,
wherein the second reference data signal is the first reference data signal.

2 more elements

Dependencies are inferred from the claim text.

Wide band clock data recovery

Life of this patent

Wide band clock data recovery

Life of this patent

Abstract

Claims11