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US 8,804,753 B2Granted
Methods and apparatus related to a shared memory buffer for variable-sized cells
AssigneeJuniper Networks, Inc.
InventorGunes Aybay
Life of this patent
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Abstract
In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank.
Claims20
A method, comprising:
- receiving at an input register a cell of an input signal, the input signal including a plurality of cells that includes the cell, the cell including a plurality of segments;
- determining whether a memory bank from a set of memory banks is a write destination of a segment from the plurality of segments when the segment is a leading segment of the cell, the set of memory banks defining at least a portion of a cut-through buffer;
- and
- modifying a flow rate of the segment through the memory bank in response to a flow control signal received at the input register.
1 more element
An apparatus, comprising:
- a write multiplexing module including a set of registers, the write multiplexing module configured to receive at a first register from the set of registers a cell including a plurality of segments,
- the write multiplexing module configured to determine that a memory bank from a set of memory banks is a write destination of a segment from the plurality of segments, the write multiplexing module configured to shift the segment from the first register from the set of registers to a second register from the set of registers when a status of a write port of the memory bank is an unavailable status.
An apparatus, comprising:
- a control module configured to trigger distribution of a set of segments included within a set of variable-sized cells to a set of memory banks within a first stage of a multi-stage switch fabric, each variable-sized cell from the set of variable-sized cells having a bit-wise width within a range of bit-wise widths,
- the control module further configured to modify a flow rate of a stream of segments from the set of segments through the set of memory banks within the first stage of a multi-stage switch fabric in response to receiving a flow control signal from a second stage of the multi-stage switch fabric downstream from the first stage of the multi-stage switch fabric,
- the control module further configured to trigger a segment from the set of segments to be sent to a memory bank from the set of memory banks within the first stage of a multi-stage switch fabric after the memory bank is determined to be a write destination of the segment.
Dependencies are inferred from the claim text.