Detector for high frequency amplitude modulation distortion
AssigneeMarvell International Ltd.
InventorsJingfeng Liu, Hoatian Zhang
Life of this patent
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Abstract
A method in a signal processor includes equalizing, with an equalizer of the signal processor, a signal corresponding to data read from a storage medium to generate an equalized signal, determining a signal level of the equalized signal, determining an expected signal level of the equalized signal, performing a comparison between the signal level of the equalized signal and the expected signal level, adjusting, after the equalized signal is output from the equalizer, an amplitude of the equalized signal by an amount determined based on the comparison of the signal level of the equalized signal and the expected signal level, and decoding the equalized signal after adjusting the amplitude of the equalized signal.
Claims21
A method in a signal processor, the method comprising:
- equalizing, with an equalizer of the signal processor, a signal corresponding to data read from a storage medium to generate an equalized signal;
- determining, in the signal processor, a signal level of the equalized signal;
- determining, in the signal processor, an expected signal level of the equalized signal;
- performing, in the signal processor, a comparison between the signal level of the equalized signal and the expected signal level;
- adjusting, in the signal processor and after the equalized signal is output from the equalizer, an amplitude of the equalized signal by an amount determined based on the comparison of the signal level of the equalized signal and the expected signal level;
- and
- decoding, in the signal processor, the equalized signal after adjusting the amplitude of the equalized signal.
An apparatus, comprising:
- an equalizer configured to generate an equalized signal by equalizing a signal corresponding to data read from a storage medium;
- a signal estimator configured to generate an estimated signal corresponding to the equalized signal;
- a first signal level detector configured to detect a level of the equalized signal;
- a second signal level detector configured to detect a level of the estimated signal;
- a gain error detector configured to generate a comparison of the level of the equalized signal and the level of the estimated signal;
- a multiplier, separate from the equalizer, configured to amplify the equalized signal by an amount determined based on the comparison;
- and
- a decoder configured to decode the equalized signal after amplification by the multiplier;
- wherein the equalizer, the signal estimator, the first signal level detector, the second signal level detector, the gain error detector, the multiplier, and the decoder are implemented using one or more integrated circuit devices.
An apparatus, comprising:
- means for equalizing a signal corresponding to data read from a storage medium to generate an equalized signal;
- means for generating an estimated signal corresponding to the equalized signal;
- means for detecting a level of the equalized signal;
- means for detecting a level of the estimated signal;
- means for generating a comparison of the level of the equalized signal and the level of the estimated signal;
- means, separate from the means for equalizing the signal, for amplifying the equalized signal by an amount determined based on the comparison;
- and
- means for decoding the equalized signal after amplification by the means for amplifying.
Dependencies are inferred from the claim text.