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US 8,804,453 B2Granted
Integrated circuit including semiconductor memory devices having stack structure
AssigneeSK hynix Inc.
InventorsJae-Bum Ko, Sang-Jin Byeon
Life of this patent
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Abstract
An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.
Claims8
An integrated circuit comprising:
- a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal;
- a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals;
- and
- a decoding operation control unit configured to control an operation of the decoding unit to activate a reserved signal or a AL-complementary setting signal in response to a stack information signal when the plurality of AL codes have a given value,
- wherein the stack information signal is activated when the integrated circuit includes a plurality of stacked semiconductor memory devices, and
- wherein the decoding operation control unit controls the decoding unit to activate the reserved signal in response to the plurality of AL codes of the given value in a case where the stack information signal is deactivated.
3 more elements
An integrated circuit comprising at least one semiconductor memory device, the semiconductor memory device comprising:
- a decoding unit configured to generate a plurality of additive latency (AL) setting signals by decoding a plurality of AL codes when a mode register is set;
- and
- a decoding operation control unit configured to control an operation of the decoding unit to activate a reserved signal or a AL-complementary setting signal in response to a stack information signal when the plurality of AL codes have a given value,
- wherein the stack information signal is activated when the integrated circuit includes a plurality of stacked semiconductor memory devices, and
- wherein the decoding operation control unit controls the decoding unit to activate the reserved signal in response to the plurality of AL codes of the given value in a case where the stack information signal is deactivated.
2 more elements
Dependencies are inferred from the claim text.