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US 8,804,450 B2Granted
Memory circuits having a diode-connected transistor with back-biased control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSteven Swei, David B. Scott
Life of this patent
Estimating the term…
Abstract
A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.
Claims20
A memory circuit comprising:
- at least one memory array;
- at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage;
- at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line;
- and
- a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.
2 more elements
A system comprising:
- a processor;
- and
- a memory circuit electrically coupled to the processor, the memory circuit comprising:
- at least one memory array;
- at least one sleep transistor electrically coupled to both the at least one memory array and a first power line for providing a first power voltage;
- at least one diode-connected transistor is turned on and electrically coupled to both the at least one memory array and the first power line during an entire period of operation;
- and
- a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.
5 more elements
Dependencies are inferred from the claim text.