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US 8,804,449 B2Granted
Apparatus and methods to provide power management for memory devices
AssigneeMicron Technology, Inc.
InventorsGerald Barkley, Nicholas Hendrickson
Life of this patent
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Abstract
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
Claims25
An apparatus comprising:
- a memory core having memory cells operatively accessible via access lines, the memory core being capable of operating in multiple modes of operation including at least a lower-power read mode and a lower-latency read/write mode, wherein the lower-power read mode has lower-power consumption than the lower-latency read/write mode;
- and
- access line bias circuitry configured to set a bias level associated with a deselected access line of the memory core, wherein the bias level is set in response to mode information such that the lower-power read mode has a first bias level for deselection and the lower-latency read/write mode has a second bias level for deselection different from the first bias level.
An apparatus comprising:
- a memory core having memory cells operatively accessible via access lines, the memory core being capable of operating in multiple modes of operation including at least a lower-power read mode and a lower-latency read/write mode, wherein the lower-power read mode has lower-power consumption than the lower-latency read/write mode;
- and
- access line bias circuitry configured to set a bias level associated with a deselected access line of the memory core, wherein the bias level is set in response to mode information;
- wherein the access line bias circuitry includes a linear down regulator configured to reduce a voltage level on the deselected access line of the memory core if the mode information indicates a change in the mode of operation from the lower-latency read/write mode to the lower-power read mode.
1 more element
An apparatus, comprising:
- a plurality of memory cores having at least a first memory core and a second memory core, the memory cores being capable of operating in multiple modes of operation including at least a lower power read mode and a lower latency read/write mode, wherein the lower power read mode has lower power consumption than the lower latency read/write mode;
- first access line bias circuitry coupled to the first memory core configured to provide a bias level associated with a deselected access line of the first memory core;
- and
- second access line bias circuitry coupled to the second memory core configured to provide a bias level associated with a deselected access line of the second memory core;
- wherein the first and second access line bias circuitry are configured to operate independently of one another so that the bias level associated with the deselected access line of the first memory core is capable of being different from the bias level associated with the deselected access line of the second memory core, wherein the bias level for deselection is set in response to mode information.
2 more elements
An apparatus, comprising:
- a plurality of memory cores having at least a first memory core and a second memory core;
- first access line bias circuitry coupled to the first memory core configured to provide a bias level associated with a deselected access line of the first memory core;
- and
- second access line bias circuitry coupled to the second memory core configured to provide a bias level associated with a deselected access line of the second memory core;
- wherein the first and second access line bias circuitry are configured to operate independently of one another so that the bias level associated with the deselected access line of the first memory core is capable of being different from the bias level associated with the deselected access line of the second memory core;
- wherein the first access line bias circuitry includes a linear down regulator to reduce a voltage on the deselected access line of the first memory core using linear down regulation if mode information from a memory access device indicates that an operating mode of the first memory core is to change from a lower latency read/write mode to a lower power read mode.
3 more elements
An apparatus comprising:
- a memory access device configured to read information from and write information to a memory device, the memory access device being capable of dynamically setting a mode of operation of a memory core of the memory device to manage power consumption of the memory, wherein selectable modes of operation include at least a lower-power read mode and a lower-latency read/write mode, wherein the lower-power read mode and the lower-latency read/write mode vary by at least a bias level.
An apparatus comprising:
- a memory access device configured to read information from and write information to a memory device, the memory access device being capable of dynamically setting a mode of operation of a memory core of the memory device to manage power consumption of the memory;
- wherein the memory access device is configured to change mode of operation of the memory core from a lower-power read mode to a lower-latency read/write mode if it is determined that a mix of write operations and read operations are expected for the memory core.
A machine-implemented method comprising:
- receiving mode information from a memory access device at a memory device;
- and
- lowering a deselected access line voltage of a memory core of the memory device if the mode information indicates a mode change for the memory core from a lower-latency read/write mode of operation to a lower-power read mode of operation.
Dependencies are inferred from the claim text.