Semiconductor device having equalizing circuit equalizing pair of bit lines
AssigneePS4 Luxco S.a.r.l.
InventorTetsuaki Okahiro
Life of this patent
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Abstract
A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The word driver includes a level shift circuit for changing the operation timing of the sub word line in accordance with the VDD level, allowing a timing to complete the equalizing operation and a timing to reset the sub word line to synchronize even when the level of the VDD level is changed.
Claims20
A semiconductor device comprising:
- a memory cell array including a plurality of bit lines having at least a pair of bit lines, a plurality of sub word lines, and a plurality of memory cells disposed at intersections of the bit lines and the sub word lines;
- a sense amplifier including a first drive circuit that drives one of the pair of bit lines to a first potential, a second drive circuit that drives other one of the pair of bit lines to a second potential higher than the first potential, and an equalizing circuit that equalizes the pair of bit lines to substantially a same potential;
- a timing control circuit that generates an equalizing signal and a timing signal having an amplitude ranging from the first potential to a third potential higher than the first potential;
- an equalizing control circuit that converts a level of the equalizing signal into a fourth potential higher than the second and third potentials and supplies the equalizing signal having the fourth potential to the equalizing circuit;
- and
- a word driver that controls the sub word lines based on the timing signal,
- wherein the word driver including a timing adjustment circuit that changes an operation timing of the sub word lines in accordance with a level of the fourth potential.
A device comprising:
- a terminal supplied with a first voltage from outside of the device,
- first and second bit lines;
- a word line;
- an equalizing circuit coupled between the first and second bit lines and including a control node, the equalizing circuit connecting the first and second bit lines to each other when the first voltage is supplied to the control node thereof, and
- a word line drive circuit that drives the word line, the word line drive circuit including a first circuit section that operates on the first voltage.
A device comprising:
- first and second bit lines;
- a word line;
- an amplifier circuit coupled between the first and second bit lines and driving, when activated, one of the first and second bit lines to a first voltage and the other of the first and second bit lines to a second voltage higher than the first voltage;
- a first control circuit operating on a third voltage that is higher than the second voltage and generating an equalizing signal taking one of the first voltage and the third voltage;
- an equalizing circuit coupled between the first and second bit lines and including a control node receiving the equalizing signal, the equalizing circuit disconnecting the first and second bit lines from each other when the equalizing signal takes the first voltage and connecting the first and second bit lines to each other when the equalizing signal takes the third voltage;
- and
- a word line drive unit activating or deactivating the word line, the word line drive unit deactivating the word line at a timing depending on a variation of the third voltage.
Dependencies are inferred from the claim text.