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US 8,804,438 B2Granted
Memory device
AssigneeFreescale Semiconductor, Inc.
InventorsAshish Sharma, Amit Kumar Gupta
Life of this patent
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Abstract
A memory device that accurately tracks memory operations includes a vertical loopback for tracking a sense clock signal to a row address decoder, and read and write reference bit lines in a reference column that include loopbacks for vertically tracking a selected bit line during read and write operations. Preferably the widths of word lines and a sense line are equal to enable the sense line to horizontally track any selected word line. The memory device also includes tri-state input/output (I/O) latches to latch sense amplifier outputs. A drive circuit of the tri-state I/O latch is disabled when the output is available at the corresponding sense amplifier and enabled when the output is latched by the latch circuit.
Claims20
A memory device, comprising:
- a memory array that includes a plurality of bit line columns connected to a corresponding plurality of bit lines, wherein each bit line column includes a plurality of bit cells, and wherein the plurality of bit cells are connected to a corresponding plurality of word lines;
- a row address decoder for generating a word line enable signal for selecting at least one word line and at least one bit line for discharging;
- a plurality of sense amplifiers connected to and for sensing the plurality of bit lines;
- a reference column comprising a read reference bit line for vertical tracking of the selected at least one bit line using a first pre-defined loopback during a read operation and a write reference bit line for vertical tracking of the selected at least one bit line using a second pre-defined loopback during a write operation;
- and
- a control circuit, including:
- a pre-charge generator for generating a pre-charge signal to pre-charge the read reference bit line for the read operation, the write reference bit line for the write operation, and the selected at least one bit line;
- a clock generator for generating an internal clock signal for the row address decoder and a sense clock signal for enabling discharge of the read reference bit line during the read operation and the write reference bit line during the write operation, wherein the sense clock signal vertically tracks the internal clock signal to the row address decoder using a third pre-defined loopback;
- and
- a sense signal generator for generating a sense enable signal for activating a sense amplifier of the plurality of sense amplifiers corresponding to the selected at least one bit line for performing the read operation when the read reference bit line is discharged, wherein the sense enable signal horizontally tracks the selected at least one word line using a sense line, and wherein widths of the sense line and the at least one word line are substantially the same.
7 more elements
A memory device, comprising:
- a memory array that includes a plurality of bit line columns connected to corresponding plurality of bit lines, wherein each bit line column includes a plurality of bit cells, and wherein the plurality of bit cells are connected to a corresponding plurality of word lines;
- a row address decoder for generating a word line enable signal for selecting at least one word line of the plurality of word lines and at least one bit line of the plurality of bit lines for discharging;
- a plurality of sense amplifiers connected to and for sensing corresponding ones of the plurality of bit lines;
- a reference column comprising a read reference bit line for vertical tracking of the selected at least one bit line using a first pre-defined loopback during a read operation and a write reference bit line for vertical tracking of the selected at least one bit line using a second pre-defined loopback during a write operation;
- and
- a control circuit, including:
- a pre-charge generator for generating a pre-charge signal to pre-charge the read reference bit line for the read operation and the write reference bit line for the write operation and the selected at least one bit line;
- a clock generator for substantially simultaneously generating an internal clock signal for the row address decoder and a sense clock signal for enabling discharge of the read reference bit line during the read operation and the write reference bit line during the write operation, wherein the sense clock signal vertically tracks the internal clock signal to the row address decoder using a third pre-defined loopback;
- and
- a sense signal generator for substantially simultaneously generating a sense enable signal for activating one of the plurality of sense amplifiers corresponding to the selected at least one bit line for performing the read operation when the read reference bit line is discharged and a strobe signal for resetting the memory device when either one of the read or write reference bit lines is discharged, wherein the sense enable signal horizontally tracks the selected at least one word line using a sense line, wherein widths of the sense line and the selected at least one word line are substantially the same;
- and
- a plurality of tri-state input/output (I/O) latches connected to corresponding ones of the plurality of sense amplifiers, wherein each tri-state I/O latch includes:
- a latch circuit for latching an output of the corresponding one of the sense amplifiers;
- and
- a drive circuit for driving the latch circuit, wherein the drive circuit is enabled and disabled by the strobe signal.
12 more elements
A memory device, comprising:
- a memory array that includes a plurality of bit line columns connected to a corresponding plurality of bit lines, wherein each bit line column includes a plurality of bit cells, and wherein the plurality of bit cells are connected to a corresponding plurality of word lines;
- a row address decoder for generating a word line enable signal for selecting at least one word line and at least one bit line for discharging;
- a plurality of sense amplifiers connected to and for sensing corresponding ones of the plurality of bit lines;
- a reference column comprising a read reference bit line for vertical tracking of the selected at least one bit line using a first pre-defined loopback during a read operation and a write reference column comprising a write reference bit line for vertical tracking of the selected at least one bit line using a second pre-defined loopback during a write operation;
- and
- a control circuit, including:
- a pre-charge generator for generating a pre-charge signal to pre-charge the read reference bit line for the read operation, the write reference bit line for the write operation, and the selected at least one bit line;
- a clock generator for substantially simultaneously generating an internal clock signal for the row address decoder and a sense clock signal for enabling discharge of the read reference bit line during the read operation and the write reference bit line during the write operation, wherein the sense clock signal vertically tracks the internal clock signal to the row address decoder using a third pre-defined loopback;
- and
- a sense signal generator for generating a sense enable signal for activating the one of the plurality of sense amplifiers corresponding to the selected at least one bit line for performing the read operation when the read reference bit line is discharged, wherein the sense enable signal horizontally tracks the selected at least one word line using a sense line, wherein widths of the sense line and the selected at least one word line are substantially equal and wherein the sense line includes a plurality of dummy loads attached thereto to match the capacitance thereof with capacitance of the selected at least one word line.
7 more elements
Dependencies are inferred from the claim text.