Column select multiplexer and method for static random-access memory and computer memory subsystem employing the same
AssigneeNVIDIA Corporation
InventorsAndreas Gotterba, Joel DeWitt, Marek Smoszna
Life of this patent
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Abstract
A column select multiplexer, a method of reading data from a random-access memory and a memory subsystem incorporating the multiplexer or the method. In one embodiment, the column select multiplexer includes: (1) a first field-effect transistor having a gate coupled via an inverter to a bitline of a static random-access memory array, (2) a second field-effect transistor coupled in series with the first field-effect transistor and having a gate coupled to a column select bus of the static random-access memory array and (3) a latch having an input coupled to the first and second field-effect transistors.
Claims18
A column select multiplexer, comprising:
- a first field-effect transistor having a gate coupled via an inverter of said column select multiplexer to a bitline of a random-access memory array;
- a second field-effect transistor coupled in series with said first field-effect transistor and having a gate coupled to a column select bus of said random-access memory array;
- and
- a latch having an input coupled to said first and second field-effect transistors, wherein said inverter is not part of said latch.
A method of reading data from a bitcell of a random-access memory array, comprising:
- providing an inverted value in said bitcell from an inverter to a gate of a first field-effect transistor in a column select multiplexer;
- providing a column select signal to a gate of a second field-effect transistor in said column select multiplexer coupled in series with said first field-effect transistor;
- and
- employing said first and second field-effect transistors to impress a logical zero on an input of a latch in said column select multiplexer only when said first and second field-effect transistors are ON, wherein said inverter is not part of said latch.
A memory subsystem, comprising:
- a memory controller;
- a first random-access memory array coupled to said memory controller;
- a second random-access memory array coupled to said memory controller;
- and
- a column select multiplexer coupled to said first random-access memory array and said second random-access memory array and including:
- a first field-effect transistor having a gate coupled through an inverter to a bitline of said first random-access memory array,
- a second field-effect transistor coupled in series with said first field-effect transistor and having a gate coupled to a column select bus of said random-access memory array, and
- a latch of said column select multiplexer having an input coupled to said first and second field-effect transistors, wherein said inverter is not part of said latch.
Dependencies are inferred from the claim text.