Semiconductor memory device and operating method thereof

An operating method of a semiconductor memory device, comprising:

• performing a second Least Significant Bit (LSB) program loop for storing second LSB data in memory cells coupled to a second word line of a plurality of word lines and for raising threshold voltages of over-erased memory cells lower than an over-erase reference voltage of a negative potential, among the memory cells coupled to the second word line, to be higher than the over-erase reference voltage;
• performing a first Most Significant Bit (MSB) program loop for storing first MSB data in memory cells coupled to a first word line adjacent to the second word line on one side, among the plurality of word lines;
• performing a third LSB program loop for storing third LSB data in memory cells coupled to a third word line adjacent to the second word line on the other side;
• and
• performing a second MSB program loop for storing second MSB data in the memory cells coupled to the second word line.

A semiconductor memory device, comprising:

• a memory block comprising memory cells coupled to word lines;
• an operation circuit configured to perform a first Least Significant Bit (LSB) program loop for memory cells included in an even page of a word line, selected from the word lines, a second LSB program loop for memory cells included in an odd page of the selected word line, a first Most Significant Bit (MSB) program loop for the memory cells of the even page, and a second MSB program loop for the memory cells of the odd page;
• and
• a control circuit configured to control the operation circuit to detect over-erased memory cells having threshold voltages lower than an over-erase reference voltage of a negative potential, among the memory cells of the odd page, and raise the threshold voltages to be higher than the over-erase reference voltage while storing LSB data in the memory cells of the odd page in the second LSB program loop.

A semiconductor memory device, comprising:

• a memory block comprising memory cells coupled to word lines;
• an operation circuit configured to perform a second Least Significant Bit (LSB) program loop for memory cells coupled to a second word line of the word lines, a first Most Significant Bit (MSB) program loop for memory cells coupled to a first word line adjacent to the second word line on one side, a third LSB program loop for memory cells coupled to a third word line adjacent to the second word line on the other side, and a second MSB program loop for the memory cells coupled to the second word line;
• and
• a control circuit configured to control the operation circuit to detect over-erased memory cells having threshold voltages lower than an over-erase reference voltage of a negative potential, among the memory cells coupled to the second word line, and raise the threshold voltages to be higher than the over-erase reference voltage while storing LSB data in the memory cells coupled to the second word line.