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US 8,804,432 B2Granted
Sensing for all bit line architecture in a memory device
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Giovanni Santin, Tommaso Vali
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Abstract
Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
Claims21
A method for sensing in a memory device, the method comprising:
- performing a sense operation of a plurality of sense operations on a data line while the data line is at a certain constant voltage level;
- and
- maintaining the data line at the certain constant voltage level between the plurality of sense operations.
A method for sensing in a memory device, the method comprising:
- selecting a first word line coupled to a plurality of selected memory cells;
- applying a voltage to each of a plurality of bit lines wherein each bit line is coupled to a different one of the plurality of selected memory cells;
- sensing, substantially simultaneously, one of a current or a voltage from the selected memory cells on each of the plurality of bit lines;
- determining data stored in each of the plurality of selected memory cells;
- and
- maintaining the voltage on the plurality of bit lines constant while selecting a second word line.
3 more elements
A memory device comprising:
- an array of memory cells coupled to bit lines and word lines;
- and
- a plurality of sense circuits, each sense circuit coupled to a different one of the bit lines, each sense circuit comprising:
- a sense amplifier coupled to its respective bit line through a control transistor;
- a latch coupled to the sense amplifier;
- and
- a precharge circuit coupled to the sense amplifier and the latch and configured to generate a voltage having a certain voltage level that is applied to its respective bit line through the sense amplifier;
- wherein the sense amplifier comprises a circuit to maintain the certain voltage level constant on its respective bit line during and between successive sense operations.
5 more elements
Dependencies are inferred from the claim text.