Clock synchronized non-volatile memory device

A nonvolatile memory apparatus comprising:

• a nonvolatile memory array;
• a plurality of terminals including a command terminal, a clock terminal and another terminal;
• a control circuit;
• and
• a logic circuit in electrical communication with said control circuit and said other terminal,
• wherein said command terminal is capable of receiving commands which include a read command and a write command,
• wherein said clock terminal is capable of receiving a clock signal,
• wherein said nonvolatile memory array includes a plurality of word lines each of which coupled to a plurality of nonvolatile memory cells,
• wherein in an operation in response to said read command received from said command terminal, said control circuit controls to selecting at least one word line, to supplying a read voltage to said at least one word line, to reading data from ones of said nonvolatile memory cells coupled to said at least one word line, and to outputting data from the logic circuit via said other terminal except said command terminal in response to said clock signal,
• wherein in an operation in response to said write command received from said command terminal, said control circuit controls to receiving data at the logic circuit via said other terminal except said command terminal in response to said clock signal, to selecting at least one word line, to supplying a program voltage to said at least one word line for writing data to at least a nonvolatile memory cell coupled to said at least one word line, to supplying a verify voltage to said at least one word line for checking whether said at least one nonvolatile memory cell is completed writing data or not, and to repeating supplying said program voltage and supplying said verify voltage to said at least one word line until said at least one nonvolatile memory cell is completed writing data,
• wherein said commands further include an erase command,
• wherein in an operation in response to said erase command received from said command terminal, said control circuit controls to selecting at least one word line, and to supplying an erase voltage to said at least one word line for erasing data into ones of said nonvolatile memory cells coupled to said at least one word line,
• wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
• wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
• wherein said control circuit comprises a circuit,
• wherein in said operation in response to said read command, said circuit senses a status of data according to a threshold voltage of said at least one nonvolatile memory cell coupled to said at least one word line which is within said threshold voltage range indicating said erase state or said threshold voltage range indicating said program state,
• wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said at least one word line to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and
• wherein said control circuit controls moving said threshold voltage of said at least one nonvolatile memory cell to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said at least one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.

A nonvolatile memory apparatus comprising:

• a control circuit;
• a first terminal;
• a second terminal;
• a third terminal;
• a logic circuit in electrical communication with said control circuit and the second terminal, and
• a nonvolatile memory array including a plurality of word lines and a plurality of nonvolatile memory cells,
• wherein said first terminal is capable of receiving a clock signal,
• wherein said second terminal is capable of receiving data in response to said clock signal and supplying data in response to said clock signal,
• wherein said third terminal is capable of receiving information for specifying an arbitrary one of operations which include an erase operation, a read operation and a program operation,
• wherein when receiving information for specifying said erase operation via said third terminal, said control circuit controls to selecting at least one word line, and to supplying an erase voltage to said at least one word line for erasing data into ones of said nonvolatile memory cells coupled to said at least one word line,
• wherein when receiving information for specifying said read operation via said third terminal, said control circuit controls to selecting at least one word line, to supplying a read voltage to said at least one word line, to reading data from ones of said nonvolatile memory cells coupled to said at least one word line, and to outputting data from the logic circuit via said second terminal except said third terminal,
• wherein when receiving information for specifying said program operation via said third terminal, said control circuit controls to receiving data at the logic circuit via said second terminal except said third terminal, to selecting at least one word line, to supplying a program voltage to said at least one word line for writing data to at least one nonvolatile memory cell coupled to said at least one word line, to supplying a verify voltage to said at least one word line for checking whether said at least one nonvolatile memory cell coupled to said at least one word line is completed writing data or not, and to repeating supplying said program voltage an supplying said verify voltage to said at least one word line until said at least one nonvolatile memory cell is completed writing data,
• wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
• wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state, and
• wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said at least one word line to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and wherein said control circuit controls moving said threshold voltage of said at least one nonvolatile memory cell coupled to said at least one word line to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said at least one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.

A nonvolatile memory apparatus comprising:

• a control circuit;
• a first terminal;
• a second terminal;
• a third terminal;
• a logic circuit in electrical communication with said control circuit and said second terminal;
• and
• a nonvolatile memory array including a plurality of word lines and a plurality of nonvolatile memory cells,
• wherein said first terminal is capable of receiving a clock signal,
• wherein said second terminal is capable of receiving data in response to said clock signal and supplying data in response to said clock signal,
• wherein said third terminal is capable of receiving information for specifying an arbitrary one of operations which include an erase operation, a read operation and a program operation,
• wherein when receiving information for specifying said erase operation via said third terminal, said control circuit controls to selecting at least one word line, and to supplying an erase voltage to said at least one word line for erasing data into ones of said nonvolatile memory cells coupled to said one word line,
• wherein when receiving information for specifying said read operation via said third terminal, said control circuit controls to selecting at least one word line, to supplying a read voltage to said at least one word line, to reading data from ones of said nonvolatile memory cells coupled to said at least one word line, and to outputting data from the logic circuit via said second terminal except said third terminal,
• wherein when receiving information for specifying said program operation via said third terminal, said control circuit controls to receiving data at the logic circuit via said second terminal except said third terminal, to selecting at least one word line, to supplying a program voltage to said at least one word line for writing data to at least one nonvolatile memory cell coupled to said at least one word line, to supplying a verify voltage to said at least one word line for checking whether said at least one nonvolatile memory cell coupled to said at least one word line is completed writing data or not, and to repeating supplying said program voltage and supplying said verify voltage to said at least one word line until said at least one nonvolatile memory cell is completed writing data,
• wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
• wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
• wherein said control circuit comprises a circuit,
• wherein when receiving information for specifying said read operation, said circuit senses status of data according to a threshold voltage of said at least one nonvolatile memory cell coupled to said at least one word line which is within said threshold voltage range indicating said erase state or said threshold voltage range indicating said program state,
• wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said at least one word line to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and
• wherein said control circuit controls moving said threshold voltage of said at least one nonvolatile memory cell to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.

A nonvolatile memory apparatus comprising:

• a control circuit;
• a clock terminal;
• a command terminal;
• a data terminal;
• a logic circuit in electrical communication with said control circuit and said data terminal;
• and
• a nonvolatile memory array including a plurality of nonvolatile memory cells and a plurality of word lines, each of which is coupled to corresponding ones of said nonvolatile memory cells,
• wherein said clock terminal receives a clock signal,
• wherein said data terminal receives data for transferring to the logic circuit in response to said clock signal and outputs data from the logic circuit in response to said clock signal,
• wherein said command terminal receives commands which include a read command and a program command,
• wherein in an operation in response to said read command received from said command terminal, said control circuit controls to selecting at least one word line, to supplying a read voltage to said at least one word line, to reading data from ones of said nonvolatile memory cells coupled to said at least one word line, and to outputting data from the logic circuit via said data terminal except said command terminal,
• wherein in an operation in response to said program command received from said command terminal, said control circuit controls to receiving data at the logic circuit via said data terminal except said command terminal, to selecting at least one word line, to supplying a program voltage to said at least one word line for writing data to at least one nonvolatile memory cell coupled to said at least one word line, to supplying a verify voltage to said at least one word line for checking whether said at least one nonvolatile memory cell is completed writing data or not, and to repeating supplying said program voltage and supplying said verify voltage to said at least one word line until said at least one nonvolatile memory cell is completed writing data,
• wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges,
• wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,
• wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said at least one word line to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and
• wherein said control circuit controls moving said threshold voltage of said at least one nonvolatile memory cell coupled to said at least one word line to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said at least one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.