Selected word line dependent select gate diffusion region voltage during programming

A non-volatile storage device comprising:

• a plurality of NAND strings, each NAND string having a plurality of non-volatile storage elements over a channel region, a first select transistor at a first end of the NAND string, and a second select transistor at a second end of the NAND string, the first select transistor of each of the NAND strings having a first diffusion region on the side of the first select transistor that is furthest from the non-volatile storage elements of the respective NAND string, the second select transistor of each of the NAND strings having a second diffusion region on the side of the second select transistor that is furthest from the non-volatile storage elements of the respective NAND string;
• a plurality of word lines associated with the plurality of NAND strings;
• and
• one or more managing circuits in communication with the plurality of NAND strings and the plurality of word lines, the one or more managing circuits apply a voltage to the first diffusion region of at least one of the first select transistors, the magnitude of the voltage applied to the first diffusion region depends on the location of a selected word line on the plurality of NAND strings, the one or more managing circuits apply a program voltage to the selected word line while applying the voltage to the first diffusion region of at least one of the first select transistors.

A 3D non-volatile storage device comprising:

• a three-dimensional memory array having:
• a plurality of NAND strings, each NAND string having a plurality of non-volatile storage elements over a channel region, a first select transistor at a first end of the NAND string, and a second select transistor at a second end of the NAND string, the first select transistor of each of the NAND strings having a first diffusion region on the side of the first select transistor that is furthest from the non-volatile storage elements of the respective NAND string, the second select transistor of each of the NAND strings having a second diffusion region on the side of the second select transistor that is furthest from the non-volatile storage elements of the respective NAND string;
• a plurality of word lines associated with the plurality of NAND strings;
• and
• one or more managing circuits in communication with the plurality of NAND strings and the plurality of word lines, the one or more managing circuits apply a voltage to the first diffusion region of at least one of the first select transistors, the magnitude of the voltage applied to the first diffusion region depends on the location of a selected word line on the plurality of NAND strings, the one or more managing circuits apply a program voltage to the selected word line while applying the voltage to the first diffusion region of at least one of the first select transistors.