Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorFumihiro Kono
Life of this patent
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Abstract
At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.
Claims15
A semiconductor memory device, comprising:
- a memory unit including a plurality of memory cores divided into a plurality of columns, each of the memory cores including bit lines, word lines, and a plurality of memory cells, each of the memory cells capable of storing multiple bits of data;
- a row decoder configured to select the word lines in the memory core according to an address signal;
- column control circuits configured to control input/output of data to/from the plurality of memory cells via the bit lines;
- and
- a control circuit configured to control the row decoder and the column control circuits,
- at least one of the plurality of columns being an LM column for storing LM flag data indicating a progression state of a write operation of the multiple bits of data, and
- each of the column control circuits being configured to execute an LM address scan operation for confirming whether the LM column exists in a corresponding one of the memory cores or not, and then stores a result of the LM address scan operation in a register,
- in various kinds of operations after the LM address scan operation, each of the column control circuits being operative to execute an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data stored in the register is first data, and omit executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data stored in the register is second data.
A semiconductor memory device, comprising:
- a memory unit including a plurality of memory cores divided into a plurality of columns, each of the memory cores including bit lines, word lines, and a plurality of memory cells, the memory cells capable of storing multiple bits of data;
- a row decoder;
- column control circuits corresponding to the plurality of memory cores respectively;
- and
- a control circuit configured to control the row decoder and the column control circuits,
- at least one of the plurality of columns being an LM column for storing LM flag data indicating a progression state of a write operation of the multiple bits of data, and
- the column control circuit being configured to execute an LM address scan operation for detecting the memory cores where existence of the LM column,
- after the LM address scan operation, each of the column control circuits being operative to execute an operation of reading the LM flag data only in the memory cores where existence of the LM column.
A method of control in a semiconductor memory device, the semiconductor device comprising a plurality of memory cores divided into a plurality of columns, the method of control comprising:
- executing an LM address scan operation that sequentially reads the plurality of columns and detects a first memory core where an LM column exists;
- executing an operation of reading LM flag data from the LM column in the first memory core;
- and
- omitting an operation of reading LM flag data from the LM column in another memory core different from the first memory core.
Dependencies are inferred from the claim text.