Nonvolatile memory device including dummy memory cell and program method thereof

A nonvolatile memory device, comprising:

• a ground select transistor;
• a dummy memory cell serially connected to the ground select transistor and configured to receive a disturbance prevention voltage via a dummy word line;
• and
• first, second and third memory cells serially connected to the dummy memory cell and configured to form a channel according to voltages received via respective first, second and third word lines,
• wherein during a program operation, the disturbance prevention voltage applied to the dummy memory cell is set according to a distance between the dummy memory cell and a memory cell selected from the first, second and third memory cells for programming,
• wherein a distance between the first memory cell and the dummy memory cell is a first distance, a distance between the second memory cell and the dummy memory cell is a second distance, and a distance between the third memory cell and the dummy memory cell is a third distance,
• wherein the third distance is longer than the second distance, and the second distance is longer than the first distance,
• wherein a first disturbance prevention voltage applied to the dummy word line when the first memory cell is selected for programming is greater than a second disturbance prevention voltage applied to the dummy word line when the second memory cell is selected for programming, and the second disturbance prevention voltage is greater than a third disturbance prevention voltage applied to the dummy word line when the third memory cell is selected for programming, and
• wherein when memory cells serially connected beyond the third memory cell are selected for programming, disturbance prevention voltages applied to the dummy word line do not increase.

A nonvolatile memory device comprising:

• a plurality of memory cells configured to form a channel responsive to first voltages received via respective word lines;
• a dummy memory cell serially connected between a ground select transistor and the plurality of memory cells, and configured to receive a disturbance prevention voltage via a dummy word line;
• and
• a voltage generator configured to generate the first voltages and a plurality of n voltage levels, selectively apply the plurality of n voltage levels as the disturbance prevention voltage to the dummy memory cell via the dummy word line, and apply the first voltages to the plurality of memory cells via the respective word lines,
• the voltage generator preventing unselected memory cells from being programmed by setting the disturbance prevention voltage according to a distance between the dummy memory cell and a memory cell selected for programming,
• wherein the plurality of n voltage levels applied to the dummy memory cell as the disturbance prevention voltage are decreased as the distance between the selected memory cell and the dummy memory cell is increased, and wherein n is greater than 2, and
• wherein the voltage levels do not increase as the distance increases beyond n greater than 2.