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US 8,804,416 B2Granted
Memory devices having select gates with p type bodies, memory strings having separate source lines and methods
AssigneeMicron Technology, Inc.
InventorAkira Goda
Life of this patent
Estimating the term…
Abstract
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
Claims18
A memory device, comprising:
- a memory cell string including:
- an elongated n type body region, having a first and second upward facing end, with a p type source region coupled to the first upward facing end, and a p type drain region coupled to the second upward facing end;
- a plurality of memory cell gates along a length of the elongated n type body region, each of the memory cell gates being separated from the elongated n type body region by at least a charge storage structure;
- a drain select gate;
- a source select gate, wherein the source select gate is shared with an adjacent memory cell string;
- and
- a data line coupled to the drain region;
- and
- a source line coupled to the source region, wherein the source line is not shared with the adjacent memory cell string.
6 more elements
A memory device, comprising:
- a memory cell string including:
- an elongated n type body region, having a first and second end, with a p type source region coupled to the first end, and a p type drain region coupled to the second end;
- a plurality of memory cell gates along a length of the elongated n type body region, each of the memory cell gates being separated from the elongated n type body region by at least a charge storage structure;
- a drain select gate;
- a source select gate, wherein the source select gate is shared with an adjacent memory cell string;
- and
- a data line coupled to the drain region;
- and
- a source line coupled to the source region, wherein the source line is not shared with the adjacent memory cell string.
6 more elements
An electronic device, comprising:
- a processor;
- a memory device coupled to the processor, including a number of memory cell strings wherein at least some of the memory cell strings include:
- an elongated n type body region, having a first and second end, with a p type source region coupled to the first end, and a p type drain region coupled to the second end;
- a plurality of memory cell gates along a length of the elongated n type body region, each of the memory cell gates being separated from the elongated n type body region by at least a charge storage structure;
- a drain select gate;
- a source select gate, wherein the source select gate is shared with an adjacent memory cell string;
- and
- a data line coupled to the drain region;
- and
- a source line coupled to the source region, wherein the source line is not shared with the adjacent memory cell string.
7 more elements
A memory device, comprising:
- a memory cell string including:
- an elongated n type body region, having a first and second end, with a p type source region coupled to the first end, and a p type drain region coupled to the second end;
- a plurality of memory cell gates along a length of the elongated n type body region, each of the memory cell gates being separated from the elongated n type body region by at least a charge storage structure;
- a drain select gate;
- a source select gate;
- and
- a data line coupled to the drain region wherein the data line is ohmically coupled to the drain region through a p+ region;
- and
- a source line coupled to the source region.
6 more elements
Dependencies are inferred from the claim text.