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US 8,804,407 B1Granted
PMOS pass gate
AssigneeAltera Corporation
InventorsJun Liu, Albert Ratnakumar, Irfan Rahim, Qi Xiang
Life of this patent
Estimating the term…
Abstract
An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.
Claims20
An integrated circuit (IC) comprising:
- a memory cell;
- and
- a pass gate coupled to the memory cell, wherein the pass gate comprises a p-channel metal oxide semiconductor (PMOS) transistor.
An integrated circuit (IC) comprising:
- a configuration random access memory (RAM), wherein the configuration RAM includes a memory cell;
- and
- a pass gate coupled to the memory cell, wherein the pass gate is a routing pass gate and comprises a p-channel metal oxide semiconductor (PMOS) transistor, further wherein the memory cell is coupled to a gate of the pass gate and data stored in the memory cell determines a state of the pass gate.
An integrated circuit (IC) comprising:
- a configuration random access memory (RAM), wherein the configuration RAM includes a memory cell, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a p-channel metal oxide semiconductor (PMOS) transistor;
- and
- a pass gate coupled to the memory cell, wherein the pass gate is a routing pass gate and comprises a PMOS transistor, further wherein the memory cell is coupled to a gate of the pass gate and data stored in the memory cell determines a state of the pass gate, further wherein the PMOS transistor of the pass gate has a negative threshold voltage.
Dependencies are inferred from the claim text.