Memory device and semiconductor device

A memory device comprising:

• a first clocked inverter electrically connected to a first line configured to be supplied with a first clock signal and a second line configured to be supplied with an inverted signal of the first clock signal;
• a first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first clocked inverter;
• a second clocked inverter electrically connected to a third line configured to be supplied with a second clock signal and a fourth line configured to be supplied with an inverted signal of the second clock signal, wherein an input terminal of the second clocked inverter is electrically connected to an output terminal of the first inverter, and an output terminal of the second clocked inverter is electrically connected to the output terminal of the first clocked inverter and the input terminal of the first inverter;
• a transistor, wherein one of a source and a drain of the transistor is electrically connected to the output terminal of the first clocked inverter, the input terminal of the first inverter, and the output terminal of the second clocked inverter;
• and
• a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor,
• wherein the transistor comprises an oxide semiconductor in a channel formation region.

A memory device comprising:

• a memory element comprising a plurality of inverters configured to hold one-bit data;
• a transistor, wherein one of a source and a drain of the transistor is electrically connected to the memory element;
• and
• a capacitor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor,
• wherein the plurality of inverters comprises a first clocked inverter and a second clocked inverter,
• wherein the first clocked inverter is configured to be controlled by a first clock signal,
• wherein the second clocked inverter is configured to be controlled by a second clock signal,
• wherein the first clocked inverter is configured to be controlled independently of the second clocked inverted, and
• wherein the transistor comprises an oxide semiconductor in a channel formation region.