Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising:

• a memory cell array including a plurality of first lines and a plurality of second lines that intersect one another, and a plurality of memory cells provided at each of intersections of the plurality of first lines and the plurality of second lines;
• and
• a control circuit for applying a voltage to the plurality of first lines and the plurality of second lines,
• each of the memory cells including a variable resistance element and a rectifier element connected in series, and having one of the first lines connected to an anode side of said rectifier element and one of the second lines connected to a cathode side of said rectifier element,
• and, when it is assumed that one of the memory cells which is to be an access target is a selected memory cell, one of the first lines connected to the selected memory cell is a selected first line, a remaining one of the first lines is an unselected first line, one of the second lines connected to the selected memory cell is a selected second line, one of the second lines adjacent to the selected second line is an adjacent unselected second line, and a remaining one of the second lines is an unselected second line,
• the control circuit applying a selected first line voltage to the selected first line and an unselected first line voltage which is larger than the selected first line voltage to the unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to the selected second line, an adjacent unselected second line voltage which is smaller than the selected second line voltage to the adjacent unselected second line, and an unselected second line voltage which is smaller than the adjacent unselected second line voltage to the unselected second line.

A nonvolatile semiconductor memory device, comprising:

• a memory cell array including a plurality of first lines and a plurality of second lines that intersect one another, and a plurality of memory cells provided at each of intersections of the plurality of first lines and the plurality of second lines;
• and
• a control circuit for applying a voltage to the plurality of first lines and the plurality of second lines,
• each of the memory cells including a variable resistance element and a rectifier element connected in series, and having one of the first lines connected to an anode side of said rectifier element and one of the second lines connected to a cathode side of said rectifier element,
• and, when it is assumed that one of the memory cells which is to be an access target is a selected memory cell, one of the first lines connected to the selected memory cell is a selected first line, one of the first lines adjacent to the selected first line is an adjacent unselected first line, a remaining one of the first lines is an unselected first line, one of the second lines connected to the selected memory cell is a selected second line, one of the second lines adjacent to the selected second line is an adjacent unselected second line, and a remaining one of the second lines is an unselected second line,
• the control circuit applying a selected first line voltage to the selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to the adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to the unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to the selected second line, an adjacent unselected second line voltage which is smaller than the selected second line voltage to the adjacent unselected second line, and an unselected second line voltage which is smaller than the adjacent unselected second line voltage to the unselected second line.