Non-volatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsKikuko Sugimae, Reika Ichihara
Life of this patent
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Abstract
A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.
Claims20
A non-volatile semiconductor memory device comprising:
- a memory cell array including one or more first wires, one or more memory cells stacked on the first wires, and one or more second wires intersecting the first wires on the memory cells, the memory cells brought into a low resistance state by application of voltage of a first polarity, and brought into a high resistance state by application of voltage of a second polarity different from the first polarity;
- and
- a control circuit configured to cause the memory cell to transition between the high resistance state and the low resistance state through the first wires and the second wires,
- wherein when performing a set operation for setting the memory cell to the low resistance state so that a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit is configured to repeat:
- applying a first voltage of the first polarity to the memory cell;
- a verify read to verify whether the resistance value of the memory cell has become lower than the predetermined resistance value;
- after the verify read, applying a second voltage of the second polarity to the memory cell;
- and
- if the verify read indicates the resistance value of the memory cell has not become lower than the predetermined resistance value, applying the first voltage again.
A non-volatile semiconductor memory device comprising:
- a memory cell array including one or more first wires, one or more memory cells stacked on the first wires, and one or more second wires intersecting the first wires on the memory cells, the memory cells are brought into a low resistance state by application of voltage of a first polarity, and are brought into a high resistance state by application of voltage of a second polarity different from the first polarity;
- and
- a control circuit configured to cause the memory cell to transition between the high resistance state and the low resistance state through the first wires and the second wires;
- wherein when performing a set operation for setting the memory cell to the low resistance state, so that a resistance value of the memory cell becomes lower than a predetermined resistance value, after applying a first voltage of the first polarity to the memory cell, the control circuit is configured to:
- perform an additional set sequence for an additional set operation on the memory cell by applying an additional set voltage of the first polarity to the memory cell, and then applying an additional reset voltage of the second polarity to the memory cell;
- and
- perform a verify read to verify whether the resistance value of the memory cell has become lower than the predetermined resistance value.
A non-volatile semiconductor memory device comprising:
- a memory cell array including one or more first wires, one or more memory cells stacked on the first wires, and one or more second wires intersecting the first wires on the memory cells, the memory cells brought into a low resistance state by application of voltage of a first polarity, and brought into a high resistance state by application of voltage of a second polarity different from the first polarity;
- and
- a control circuit configured to cause the memory cell to transition between the high resistance state and the low resistance state through the first wires and the second wires,
- wherein when performing a set operation for setting the memory cell to the low resistance state, the control circuit is configured to:
- apply a first voltage for setting to the memory cell;
- and
- perform a verify read for verifying whether a resistance value of the memory cell has become lower than a predetermined resistance value, by applying a verify read voltage to the memory cell;
- and
- apply a verify compensation voltage of a polarity different from that of the verify read voltage after applying the verify read voltage to the memory cell.
Dependencies are inferred from the claim text.