Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator
AssigneeRambus Inc.
InventorsMarko Aleksic, Brian S. Leibowitz
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AssigneeRambus Inc.
InventorsMarko Aleksic, Brian S. Leibowitz
Estimating the term…
Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
A circuit, comprising:
A controller device that controls the operation of a memory device, the controller device comprising:
A method for determining a phase boundary between two adjacent phase tuning ranges, comprising:
A circuit, comprising:
Dependencies are inferred from the claim text.
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Automatic control of frequency or phase; Synchronisation: using a reference signal directly applied to the generator
Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal…
Details of the phase-locked loop: provided with an additional controlled phase shifter
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop
About 6 years 3 months of term left · ends 3 Feb 2033 (estimated)
This disclosure generally relates to electronic circuits. This disclosure generally relates to integrated circuit devices that include an injection-locked oscillator (ILO) circuit.
Some applications (e.g., high-performance memory systems) use circuits for adjusting the phase of a clock signal. An injection-locked oscillator (ILO) can be used in a phase adjustment circuit that adjusts the phase of a clock signal with respect to a reference phase. Some ILO-based phase adjustment circuits add a significant amount of complex circuitry to adjust the phase of the output clock signal.
FIG. 1 illustrates an ILO-based clock deskew circuit in accordance with some embodiments described in this disclosure.
FIG. 2 illustrates signal waveforms associated with an ILO-based clock deskew circuit in accordance with some embodiments described in this disclosure.
FIG. 3A illustrates an ILO-based clock deskew circuit in accordance with some embodiments described in this disclosure.
Embodiments presented in this disclosure are directed to methods and apparatuses featuring a circuit that uses an ILO to adjust the phase of a clock signal. In some embodiments, the ILO locks onto an input clock signal if the frequency of the input clock signal is relatively close to the free-running frequency of the ILO, or relatively close to a sub-harmonic or a super-harmonic of the free-running frequency of the ILO. In some embodiments, the phase of an output clock signal can be adjusted by varying the difference between an injection clock signal frequency (which can be the same as the input clock signal frequency) and the free-running frequency of the ILO. Specifically, in some embodiments, the ILO-based clock deskew circuit can be calibrated so that a free-running frequency of the ILO can be established for a target phase value, thereby enabling the ILO-based clock deskew circuit to output the clock signal with the target phase by tuning the ILO to the determined free-running frequency. In some embodiments, the ILO-based clock deskew circuit can include detection circuitry that is capable of detecting a phase boundary between adjacent phase tuning ranges. In this disclosure, unless otherwise stated, the phrase “based on” means “based solely or partly on.”
Embodiments described herein include, but are not limited to, ILOs that are based on a tank circuit (i.e., an inductor/capacitor oscillator) or a ring oscillator, with one or more nodes for receiving an input clock signal, and one or more nodes for outputting an output clock signal.
FIG. 1 illustrates an ILO-based clock deskew circuit in accordance with some embodiments described in this disclosure.