Stacked memory with redundancy

A method of operation in a stacked memory, the method comprising:

• receiving a read data request from a memory controller;
• accessing read data from a plurality of stacked integrated circuit memory chips, a portion of the read data stored in a redundant memory;
• internally transferring the portion of the read data from the redundant memory to a selected one of the plurality of stacked integrated circuit memory chips;
• and
• externally transferring the read data from the selected one of the stacked integrated circuit memory chips to the memory controller.

A method of operation in a stacked memory, the method comprising:

• storing address information in a first portion of a redundant memory, the address information associated with a substituted storage area, the substituted storage area residing in a first integrated circuit memory chip stacked with the redundant memory;
• storing data in a second portion of the redundant memory, the data corresponding to the address information;
• and
• steering accesses to the data based on the address information.

A memory module comprising:

• a substrate having a databus for coupling to a memory controller;
• a plurality of stacked memories disposed on the substrate, each of the stacked memories including
• a first integrated circuit memory chip having first storage locations,
• a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip, the second integrated circuit memory chip having second storage locations,
• a redundant memory shared by the first and second integrated circuit memory chips, the redundant memory having redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory devices,
• an external connection interface for coupling to the databus,
• a first signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the first signal path coupled to the external connection interface, and
• a second signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the second signal path coupled to the external connection interface via the first signal path.