Electrostatic discharge protection circuit having buffer stage FET with thicker gate oxide than common-source FET
AssigneeTexas Instruments Incorporated
InventorJonathan Brodsky
Life of this patent
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Abstract
An active-FET ESD cell (300) for protecting an I/O pad (301) includes a first MOS transistor (310) with a gate oxide (315) of a first thickness and a second MOS transistor (320) with a gate oxide (325) of a second thickness greater than the first thickness at least by the amount required to handle the source-follower threshold voltage, the first transistor having its drain (313) tied to the I/O pad, its source (311) tied to ground, and its gate (312) tied to the source (321) of the second transistor and resistively connected to ground (340), and the second transistor having its drain (323) tied to the I/O pad and its gate tied to a capacitor (330) connected to the I/O pad and to a resistor (331) connected to ground.
Claims14
A device for protecting an input/output (I/O) pad of a semiconductor integrated circuit against electrostatic discharge (ESD) events, comprising:
- a common-source stage tied to the I/O pad, and including a first drain-extended MOS transistor suitable to discharge ESD currents, the first transistor having a gate oxide of a first thickness;
- and
- a source-follower stage tied to the I/O pad by a trigger, and connected to the common-source stage, the source-follower stage including a second drain-extended MOS transistor having gate oxide of a second thickness,
- wherein the second thickness is greater than the first thickness at least by the amount required to handle the source-follower threshold voltage.
A device for protecting an input/output (I/O) pad of a semiconductor integrated circuit against electrostatic discharge events, comprising:
- a first MOS transistor having a gate oxide of a first thickness;
- and
- a second MOS transistor having a gate oxide of a second thickness at least twice as great as the first thickness;
- the first transistor having its drain tied to the I/O pad, its source tied to ground, and its gate tied to the source of the second transistor and resistively connected to ground;
- and
- the second transistor having its drain tied to the I/O pad, and its gate tied to a capacitor connected to the I/O pad, and to a resistor connected to ground.
Dependencies are inferred from the claim text.