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US 8,804,137 B2Granted
Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability
AssigneeKLA-Tencor Corporation
InventorsDongSub Choi, Amir Widmann, Zain Saidin, Frank Laske, John Robinson
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Abstract
A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.
Claims21
A method for wafer processing, comprising:
- accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:
- a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate;
- a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;
- calculating alignment error;
- and
- presenting a calculated correlation between mask data and wafer data.
3 more elements
A system comprising:
- means for accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:
- a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate, and
- a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;
- means for calculating alignment error;
- and
- means for presenting a calculated correlation between mask data and wafer data.
3 more elements
A system comprising:
- a semiconductor device layer alignment detector configured for generating alignment information;
- a processing device configured for:
- accepting alignment information from the semiconductor device layer alignment detector associated with at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:
- a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate;
- a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;
- calculating alignment error;
- and
- a presentation device configured for presenting a calculated correlation between mask data and wafer data.
5 more elements
Dependencies are inferred from the claim text.