Pixel structure having metal-insulator-semiconductor capacitor

A pixel structure, comprising:

• a scan line and a data line;
• an active device, electrically connected to the scan line and the data line;
• a pixel electrode, electrically connected to the active device;
• a capacitor electrode line, located underneath the pixel electrode;
• a semi-conductive pattern layer, disposed between the capacitor electrode line and the pixel electrode, wherein the pixel electrode is electrically connected to the semi-conductive pattern layer;
• at least one dielectric layer, disposed between the capacitor electrode line and the pixel electrode, wherein the at least one dielectric layer comprises a first dielectric layer, disposed between the semi-conductive pattern layer and the capacitor electrode line, and a second dielectric layer, covering the first dielectric layer;
• and
• a storage electrode pattern layer, disposed between the pixel electrode and the capacitor electrode line, and a portion of the storage electrode pattern layer is directly contacted with the first dielectric layer, wherein the storage electrode pattern layer is narrower than the capacitor electrode line and wider than the semi-conductive pattern layer, the storage electrode pattern layer is electrically connected to the pixel electrode,
• wherein the second dielectric layer covers the storage electrode pattern layer, the first dielectric layer and the second dielectric layer are sandwiched between the pixel electrode and the capacitor electrode line, and the first dielectric layer is sandwiched between the storage electrode pattern layer and the capacitor electrode line,
• wherein the capacitor electrode line and the pixel electrode have a first overlap region not overlapped with the semi-conductive pattern layer and the capacitor electrode line in a direction substantially normal to a surface of the semi-conductive pattern layer constitute a first storage capacitor having a first storage capacitance, the semi-conductive pattern layer and the capacitor electrode line having a second overlap region in the direction substantially normal to the surface of the semi-conductive pattern layer constitute a second storage capacitor having a second storage capacitance, and the storage electrode pattern layer and the capacitor electrode line having a third overlap region not overlapped with the semi-conductive pattern layer in the direction substantially normal to the surface of the semi-conductive pattern layer constitute a third storage capacitor having a third storage capacitance, and
• wherein a total storage capacitance is the sum of the first storage capacitance, the second storage capacitance, and the third storage capacitance, the second storage capacitance occupies 30%-80% of the total storage capacitance, and each of the first storage capacitance, the second storage capacitance, and the third storage capacitance is larger than zero.