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AssigneeSTMicroelectronics International N.V.
InventorsRavindranath Ramalingaiah Munnan, Raghu Ravindran, Ravi Shekhar
Estimating the term…
A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.
A system for determining nonlinearity characteristics of an analog-to-digital converter (ADC), comprising:
A system for determining nonlinearity characteristics of an analog-to-digital converter (ADC) configured to receive an input analog voltage and responsively produce digital codes as outputs, comprising:
A method for testing an analog-to-digital converter (ADC) using a built-in self-test, comprising:
A system, comprising:
Dependencies are inferred from the claim text.