Relaxation oscillator with self-biased comparator

A relaxation oscillator for generating an output clock signal, comprising:

• a resistor-capacitor (RC) circuit for generating first and second comparator input signals and receiving first and second control signals;
• a self-biased comparator stage connected to the RC circuit for generating first and second comparator output signals, the self-biased comparator stage comprising:
• a self-biased comparator for receiving the first and second comparator input signals and generating first and second intermediate output signals and the first and second comparator output signals, wherein the self-biased comparator comprises:
• a first input stage for receiving the first comparator input signal and generating the first intermediate output signal, wherein the first input stage includes:
• a first transistor having a source terminal for receiving a supply voltage;
• and
• a second transistor having a drain terminal connected to a drain terminal of the first transistor, and a gate terminal for receiving the first comparator input signal, wherein the first intermediate output signal is generated at the drain terminals of the first and second transistors;
• a second input stage for receiving the second comparator input signal and generating the second intermediate output signal, wherein the second input state includes:
• a third transistor having a source terminal for receiving the supply voltage;
• and
• a fourth transistor having a drain terminal connected to a drain terminal of the third transistor, a gate terminal for receiving the second comparator input signal, and a source terminal connected to a source terminal of the second transistor, wherein the second intermediate output signal is generated at the drain terminals of the third and fourth transistors;
• a voltage reference circuit for generating a voltage bias signal, wherein the voltage reference circuit comprises:
• a fifth transistor having a source terminal for receiving the supply voltage, a gate terminal connected to a gate terminal of the third transistor, and a drain terminal connected to a gate terminal of the first transistor and the gate terminal of the third transistor, wherein the voltage bias signal is generated at the drain terminal of the fifth transistor;
• and
• a sixth transistor having a drain terminal connected to the drain terminal of the fifth transistor, a gate terminal for receiving a reference voltage, and a source terminal connected to the source terminals of the second and fourth transistors;
• a seventh transistor having a drain terminal connected to the source terminals of the second, fourth, and sixth transistors;
• and
• a first resistor having a first terminal connected to a source terminal of the seventh transistor and a second terminal connected to ground;
• an eighth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the gate and drain terminals of the first and fifth transistors, respectively;
• a ninth transistor having a drain terminal connected to a drain terminal of the eighth transistor, a gate terminal connected to the drain terminal thereof and to a gate terminal of the seventh transistor, and a source terminal connected to ground;
• a tenth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the first and second transistors for receiving the first intermediate output signal;
• an eleventh transistor having a drain terminal connected to a drain terminal of the tenth transistor, a gate terminal connected to the drain terminals of the eighth and ninth transistors, and a source terminal connected to ground, wherein the first comparator output signal is generated at the drain terminals of the tenth and eleventh transistors;
• a twelfth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the third and fourth transistors for receiving the second intermediate output signal;
• and
• a thirteenth transistor having a drain terminal connected to a drain terminal of the twelfth transistor, a gate terminal connected to the gate terminals of the seventh and ninth transistors, and a source terminal connected to ground, wherein the second comparator output signal is generated at the drain terminals of the twelfth and thirteenth transistors.