Common mode bias circuit
AssigneeAnalog Devices, Inc.
InventorDaniel Rey-Losada
Life of this patent
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Abstract
A bias voltage source for a differential circuit has low output impedance at DC, but considerably higher output impedance within the frequency band of the differential signal being processed, to provide an accurate, well-matched common-mode bias voltage to each component of a differential signal path, while providing a low noise current, minimizing the conversion between common-mode and differential modes, and preserving available headroom, and all without requiring the use of large resistors.
Claims20
A biasing circuit for providing bias voltage to a differential circuit configured to process signals at frequencies above a pre-determined frequency within a signal band, the differential circuit having a first signal node and a second signal node, the first signal node and second signal node together forming a differential node, the biasing circuit comprising:
- a bias source having a DC voltage output, the DC voltage output producing a DC bias voltage and having:
- a first output impedance at DC, and
- a second output impedance at frequencies within the signal band;
- a first bias resistor having a first bias resistance, the first bias resistor coupled between the DC voltage output and the first signal node so as to provide the DC bias voltage to the first signal node;
- and
- a second bias resistor having a second bias resistance, the second bias resistor coupled between the DC voltage output and the second signal node so as to provide the DC bias voltage to the second signal node,
- wherein the magnitude of the first output impedance being less than 80 percent of the smaller of the magnitude of the first bias resistance and the magnitude of the second bias resistance, and
- the magnitude of the second output impedance being at least 20 percent of the larger of the magnitude of the first bias resistance and the magnitude of the second bias resistance, provided that the magnitude of the first output impedance is less than fifty percent of the magnitude of the second output impedance.
A differential circuit for processing signals within a signal band above a pre-determined frequency, the differential circuit comprising:
- a differential processor having a first input and a second input, the first input and second input comprising a differential input, the differential processor having a bandwidth that includes frequencies above the pre-determined frequency;
- a biasing amplifier having a bias non-inverting input, a feedback inverting input, and a bias output;
- a voltage source electrically coupled to the bias non-inverting input;
- a feedback path electrically coupling the feedback inverting input to the bias output, such that the biasing amplifier presents a closed-loop output impedance at DC, and a second output impedance at frequencies above the predetermined frequency;
- a first biasing resistance having a first terminal and a second terminal, the first terminal electrically coupled to the bias output, and the second terminal electrically coupled to the first input;
- a second biasing resistance having a third terminal and a fourth terminal, the third terminal electrically coupled to the bias output, and the fourth terminal electrically coupled to the second input,
- wherein the magnitude of the closed-loop output impedance at DC being less than ten percent of the lower of the magnitude of the first biasing resistance and the magnitude of the second biasing resistance, and
- the magnitude of the second output impedance being at least two hundred percent of the higher of the magnitude of the first biasing resistance and the magnitude of the second biasing resistance.
A method for providing a bias voltage to a differential circuit configured to process signals at frequencies within a signal band above a pre-determined frequency, the differential circuit having a first signal input and a second signal input, the first signal input and second signal input together comprising a differential node, the method comprising:
- providing a bias source having a DC bias voltage output, the DC bias voltage output having:
- a first output impedance at DC, and
- a second output impedance at frequencies within the signal band;
- providing a bias first resistance coupled between the DC bias voltage output and the first signal input so as to provide a DC bias voltage to the first signal input;
- and
- providing a second bias resistance coupled between the DC bias voltage output and the second signal input so as to provide the DC bias voltage to the second signal input,
- wherein the magnitude of the first output impedance being less than 10 percent of the smaller of the first bias resistance and the second bias resistance, and
- the magnitude of the second output impedance being at least 200 percent of the larger of the first bias resistance and the second bias resistance.
A biasing circuit for providing bias voltage to a plurality of signal nodes in a differential circuit, which differential circuit is configured to process signals at frequencies above a pre-determined frequency within a signal band, the differential circuit having a first signal node and a second signal node, the first signal node and second signal node together forming a differential node, the biasing circuit comprising:
- a bias source having:
- a DC voltage source, the DC voltage source producing a DC bias voltage, and
- an inductance having a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the DC voltage source;
- a first bias resistor having a first bias resistance, the first bias resistor coupled between the second inductor terminal and the first signal node so as to provide the DC bias voltage to the first signal node;
- and
- a second bias resistor having a second bias resistance, the second bias resistor coupled between the second inductor terminal and the second signal node so as to provide the DC bias voltage to the second signal node,
- such that the DC voltage source and the inductance form a bias source having a first output impedance at a DC, and a second output impedance within the signal band,
- wherein the magnitude of the first output impedance being less than 10 percent of the smaller of the magnitude of the first bias resistance and the magnitude of the second bias resistance, and
- the magnitude of the second output impedance being at least 200 percent of the larger of the magnitude of the first bias resistance and the second bias resistance, provided that the magnitude of the first output impedance is less than the magnitude of the magnitude of the second output impedance.
Dependencies are inferred from the claim text.