Level shifter for noise and leakage suppression

A circuit comprising:

• an input stage configured to couple to a first voltage domain;
• and
• an output stage coupled to the input stage and configured to produce complementary output signals for a second voltage domain that are based on complementary input signals and configured to couple to a second voltage domain,
• wherein an input terminal of the input stage is configured to be gated in response to a powering down of the first voltage domain and a pair of cross coupled inverters in the input stage hold the last state that is applied to input terminals of the input stage when the first voltage domain is powered down, wherein the pair of cross coupled inverters comprise transistors that are coupled to ground.

A processor circuit comprising:

• a processor core;
• a north-bridge circuit;
• and
• a level shifting circuit coupled between the processor core and the north bridge circuit, the level shifting circuit comprising:
• an input stage;
• and
• an output stage coupled to the input stage and configured to produce complementary output signals for a second voltage domain that are based on complementary input signals,
• wherein an input terminal of the input stage is configured to be gated in response to a powering down of the first voltage domain and a pair of cross coupled inverters in the input stage hold the last state that is applied to input terminals of the input stage responsive to the powering down of the first voltage domain, and wherein the pair of cross coupled inverters comprise transistors that are coupled to ground.

A level shifter circuit comprising:

• means for receiving complementary input signals coupled to a first voltage domain;
• and
• means for outputting complementary output signals for a second voltage domain that are based on the complementary input signals,
• wherein the means for receiving complementary input signals comprises means for gating the complementary input signals in direct response to a powering down of the first voltage domain and further comprises a pair of cross coupled inverters for maintaining the last state of the complementary input signals when the first voltage domain is powered down, wherein the pair of cross coupled inverters comprise transistors that are coupled to ground.

A level shifter circuit comprising:

• input circuitry comprising input terminals configured to couple with a first voltage domain;
• and
• output circuitry configured to produce complementary output signals for a second voltage domain that are based on complementary input signals,
• wherein the input circuitry comprises circuitry configured to gate input signals in response to a powering down of the first voltage domain and a pair of cross coupled inverters configured to maintain the last state of the input signals when the first voltage domain is powered down, wherein the pair of cross coupled inverters comprise transistors that are coupled to ground.