Fast flip-flop structure with reduced set-up time
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShyh-An Chi, Shiue Tsong Shen, Jeff Lee, Frank Y. Lee
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShyh-An Chi, Shiue Tsong Shen, Jeff Lee, Frank Y. Lee
Estimating the term…
A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.
A flip-flop, comprising:
A flip-flop, comprising:
A flip-flop, comprising:
Dependencies are inferred from the claim text.