Pulse width adjusting circuit and method
AssigneeInternational Business Machines Corporation
InventorsMasatoshi Ishii, Gen Yamada, Hisatada Miyatake
Life of this patent
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Abstract
The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.
Claims19
A pulse width adjusting circuit comprising:
- a pulse delaying circuit for inputting an inputted pulse signal and for outputting a plurality of different delayed pulse signals;
- a transmission gate for inputting the inputted pulse signal and controlling the passage of the inputted pulse signal in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals;
- a pulse width setting circuit connected to the transmission gate for setting a pulse width of an outputted pulse signal generated on the basis of the inputted pulse signal passing through the transmission gate;
- and
- wherein the pulse delaying circuit is an even number of four or more inverters connected in series, three different delayed pulse signals are outputted from the first, second and third inverters counting from the output end, and the two delayed pulse signals outputted from the first and second inverters are applied, respectively, to the first gate and second gate of the transmission gate.
A pulse width adjusting method comprising the steps of:
- generating a series of different delayed pulse signals from an inputted pulse signal, wherein the series of different delayed pulse signals comprises an even number of four or more delayed pulse signals;
- applying the last two delayed pulse signals from among the series of different delayed pulse signals to a transmission gate, and controlling the passage of the inputted pulse signal through the transmission gate;
- and
- setting a pulse width of the output pulse signal generated on the basis of the inputted pulse signal passing through the transmission gate to a predetermined pulse width.
Dependencies are inferred from the claim text.