Semiconductor device having duty-cycle correction circuit
OwnerKatsuhiro Kitagawainventor
Life of this patent
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Abstract
Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.
Claims16
A semiconductor device comprising:
- an input node supplied with a first clock signal;
- an output node outputting a second clock signal;
- a plurality of variable delay circuits connected in series between the input node and the output node;
- a control circuit commonly controlling the variable delay circuits based on phases of the first and second clock signals;
- and
- a mixer circuit generating a third clock signal based on one of a plurality of input clock signals and one of a plurality of output clock signals, each of the plurality of input clock signals supplied to an associated one of the variable delay circuits, and each of the plurality of output clock signals output from an associated one of the variable delay circuits.
A method of controlling a semiconductor device, the method comprising:
- generating a first clock signal by delaying an input clock signal based on a delay time;
- generating a second clock signal by delaying the first clock signal based on the delay time;
- comparing a phase of the second clock signal with a phase of the input clock signal to control the delay time;
- and
- mixing the first clock signal and the second clock signal to generate a third clock signal.
Dependencies are inferred from the claim text.