Serializer-deserializer clock and data recovery gain adjustment
AssigneeLSI Corporation
InventorsVladimir Sindalovsky, Joseph Anidjar, Lane A. Smith, Brett David Hardy
Life of this patent
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AssigneeLSI Corporation
InventorsVladimir Sindalovsky, Joseph Anidjar, Lane A. Smith, Brett David Hardy
Estimating the term…
In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.
Apparatus for a voltage-controlled oscillator based clock and data recovery circuit, the apparatus comprising:
A method of adjustment of a voltage-controlled oscillator voltage-controlled oscillator based clock and data recovery circuit, the method comprising the steps of:
A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for adjustment of a voltage-controlled oscillator based clock and data recovery circuit, comprising the steps of:
Dependencies are inferred from the claim text.