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US 8,803,572 B2Granted
Phase locked loop circuit with reduced jitter
AssigneeSTMicroelectronics International N.V.
InventorsAnand Kumar, Pradeep Dhadda
Life of this patent
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Abstract
A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.
Claims25
A circuit, comprising:
- a filter configured to produce a first filtered signal and a second filtered signal;
- and
- an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifying the second filtered signal, the difference including a scaling factor.
A circuit, comprisinq:
- a filter configured to produce a first filtered signal and a second filtered signal;
- and
- an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifying the second filtered signal;
- wherein the filter comprises:
- a low pass filter having:
- a first capacitor in series with a resistor;
- and
- a second capacitor in parallel with the first capacitor and resistor;
- and
- wherein the values of the first capacitor and resistor are scaled by a factor such that the first capacitor is reduced by the factor and the resistor is increased by the factor.
7 more elements
A circuit, comprising:
- a filter configured to produce a first filtered signal and a second filtered signal;
- and
- an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifying the second filtered signal;
- wherein the filter comprises:
- a low pass filter having:
- a first capacitor in series with a resistor;
- and
- a second capacitor in parallel with the first capacitor and resistor;
- and
- wherein the values of the first capacitor and resistor are scaled by a factor such that the first capacitor is reduced by the factor and the resistor is increased by an exponential power of two of the factor.
7 more elements
A circuit, comprising:
- a filter configured to produce a first filtered signal and a second filtered signal;
- and
- an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifying the second filtered signal;
- wherein the filter comprises:
- a low pass filter having:
- a first capacitor in series with a resistor;
- and
- a second capacitor in parallel with the first capacitor and resistor;
- and
- wherein the values of the first capacitor and resistor are scaled by a factor such that the first and second capacitors are reduced by the factor and the resistor is increased by an amount equal to a square root of the factor times the factor.
7 more elements
A circuit, comprisinq:
- a filter configured to produce a first filtered signal and a second filtered signal;
- and
- an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifyinq the second filtered signal;
- wherein the filter and the oscillator comprise a transfer function of H(s)=(1+sR1C1/M)/(s(C1+C2+sR1C1C2))*K, where s comprises a frequency of a signal, R1 comprises the resistance of a resistor, C1 comprises the capacitance of a first capacitor, C2 comprises the capacitance of a second capacitor, M comprising a scaling factor and K comprises a gain.
1 more element
A phase-locked loop, comprising:
- a phase detector;
- a charge pump coupled to the phase detector;
- a low pass filter coupled to the charge pump;
- an oscillator configured to receive a first control signal from the low pass filter and a second control signal from the low pass filter, the first control signal having a magnitude that is different by a scaling factor from the magnitude of the second control signal;
- and
- a feedback circuit coupled to the oscillator.
3 more elements
An integrated circuit, comprising:
- a filter having a resistor and a capacitor coupled to a first node
- an oscillator having a first voltage-to-current converter having a first gain and a second voltage-to-current converter having a second gain related to the first gain by a scaling factor, the first voltage-to-current converter having a control node coupled to the first node.
A system, comprising:
- a digital signal processor having a phase locked loop, comprising:
- a phase detector;
- a charge pump coupled to the phase detector;
- a low pass filter coupled to the charge pump;
- an oscillator configured to receive a first control signal from the low pass filter and a second control signal from the low pass filter, the first control signal having a magnitude that is different by a scaling factor from the magnitude of the second control signal;
- and
- a feedback circuit coupled to the oscillator.
4 more elements
A method, comprising:
- filtering a signal such that a first filtered control signal and a second filtered control signal are generated, the first filtered control signal related to the second filtered control signal by a scaling factor;
- and
- generating an oscillating signal based on the first filtered control signal and the second filtered control signal.
A method, comprising:
- generating a control signal for adjusting a phase of a signal in a phase-locked loop;
- and
- applying a transfer function to the control signal of H(s)=(1+sR1C1/M)/(s(C1+C2+sR1C1C2))*K, where s comprises a frequency of a signal, R1 comprises the resistance of a resistor, C1 comprises the capacitance of a first capacitor, C2 comprises the capacitance of a second capacitor, M comprising a scaling factor and K comprises a gain.
Dependencies are inferred from the claim text.