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US 8,803,571 B1Granted
Reset signal propagation in an integrated circuit
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorMoshe Rabinovitch
Life of this patent
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Abstract
Some of the embodiments of the present disclosure provide a integrated circuit comprising a plurality of components, wherein each of the plurality of components is configured to receive a clock signal and a reset signal; a clock module configured to selectively suppress the clock signal; and a reset module configured to assert the reset signal while the clock signal is suppressed. Other embodiments are also described and claimed.
Claims15
An integrated circuit comprising:
- a plurality of components, wherein each of the plurality of components is configured to receive a clock signal and a reset signal;
- a reset module configured to (i) assert the reset signal subsequent to a trigger event and prior to a commencement of a first time period, (ii) assert the reset signal during the first time period, and (ii) de-assert the reset signal following the first time period;
- and
- a clock module configured to (i) suppress the clock signal during the first time period, and (ii) refrain from suppressing the clock signal subsequent to the trigger event and prior to the commencement of the first time period.
1 more element
A method comprising:
- transmitting, to a plurality of components of an integrated circuit, a clock signal and a reset signal;
- asserting the reset signal (i) subsequent to a trigger event and prior to a commencement of a first time period, and (ii) during the first time period;
- de-asserting the reset signal following the first time period;
- suppressing the clock signal during the first time period;
- and
- refraining from suppressing the clock signal subsequent to the trigger event and prior to the commencement of the first time period.
3 more elements
A method comprising:
- distributing a reset signal to a plurality of components of an integrated circuit via a reset signal tree, the reset signal tree being an unbalanced signal tree;
- distributing a clock signal to the plurality of components of the integrated circuit via a clock signal tree, the clock signal tree being a balanced signal tree;
- resetting the plurality of components, by an assertion of the reset signal, such that each of the plurality of components comes out of reset during a same clock cycle;
- detecting a start-up event of the integrated circuit;
- in response to detecting the start-up event, selectively suppressing the clock signal;
- in response to detecting the start-up event, asserting the reset signal when the clock signal is selectively suppressed;
- and
- in response to detecting the start-up event, asserting the reset signal when the clock signal is not suppressed.
5 more elements
Dependencies are inferred from the claim text.