Apparatus and method for decoding an address in two stages
AssigneeRaytheon Company
InventorMartin S. Denham
Life of this patent
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Abstract
Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2N unique addresses from unique combinations of the plurality of first-stage decoded address outputs.
Claims14
An address decode circuit comprising:
- a first decoder circuit configured to partition an N-bit address of an addressable element into at least three address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit including a corresponding plurality of one-hot decoders and a corresponding plurality of sets of decode lines, each set of decode lines coupled to a respective one of the plurality of one-hot decoders, wherein the first decoder circuit is configured to first-stage decode the at least three address segments into the plurality of sets of decode lines using the plurality of one-hot decoders, each one-hot decoder configured to receive and decode one of the at least three address segments, to provide a plurality of first-stage decoded address outputs from the N-bit address, wherein only one of the plurality of first-stage decoded address outputs is enabled at any given time;
- and
- a second orthogonal decoder circuit coupled to the plurality of sets of decode lines and configured to receive the plurality of first-stage decoded address outputs and to produce 2N unique decoded addresses at 2N address outputs from unique combinations of the plurality of first-stage decoded address outputs, each one of the 2N address outputs corresponding to one unique decoded address within the addressable element derived from the N-bit address.
A method of decoding an N-bit binary address of an addressable element, N being a positive integer, the method comprising:
- partitioning the N-bit address into at least three address segments, each address segment including fewer than N bits;
- decoding each of the at least three address segments using a one-hot decoding process to provide corresponding a plurality of groups of first-stage decodes, each group of first stage decodes corresponding to one of the plurality of address segments, wherein only one first-stage decode in each group of first-stage decodes in enabled at any given time;
- projecting the plurality of groups of first-stage decodes over a second-stage decode region corresponding to the addressable element;
- and
- producing 2N unique decoded addresses at 2N address outputs, each one of the 2N address outputs corresponding to one unique decoded address derived from the N-bit address, from exhaustive combinations of one first-stage decode from each of the plurality of groups of first-stage decodes.
An address decode circuit configured to decode an address of N address bits, N being a positive integer, the address decode circuit comprising:
- a plurality of one-hot decoders each configured to receive and decode one of at least three address segments, each address segment including at least one address bit and wherein a sum of the address bits in the at least three address segments is N;
- a corresponding plurality of sets of wires connected to the plurality of one-hot decoders, each one-hot decoder connected to one set of wires, and each set of wires including at least two wires, each one-hot decoder configured to enable one wire in the respective set of wires for every combination of the address bits in the corresponding address segment;
- and
- an orthogonal decoder circuit comprising 2N NAND gates, each NAND gate connected to one wire from each set of wires for each of the decoders in the plurality of one-hot decoders, wherein an output of each NAND gate corresponds to a particular combination of the N address bits describing one unique decoded address of an addressable element derived from the address of N address bits.
Dependencies are inferred from the claim text.