Back to results
US 8,803,552 B2Granted
Reconfigurable sequencer structure
AssigneePact Xpp Technologies AG
InventorMartin Vorbach
Life of this patent
Estimating the term…
Abstract
A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
Claims4
A data processor chip comprising:
- a plurality of data processing elements each including at least one arithmetic-logic-unit;
- a plurality of memory elements adapted for storing at least one of program data and program code;
- at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals;
- and
- a bus system;
- wherein:
- each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;
- the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system at runtime;
- and
- each of the data processing, memory, and input/output elements is flexibly connectable for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system at runtime.
7 more elements
A data processor chip comprising:
- a plurality of data processing elements each including at least one arithmetic-logic unit;
- a plurality of memory elements adapted for storing at least one of program data and program code;
- at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals;
- and
- a bus system;
- wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;
- the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system;
- and
- each of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system.
6 more elements
A computer system including:
- a data processor chip having a plurality of data processing elements each including at least one arithmetic-logic unit;
- a plurality of memory elements adapted for storing at least one of program data and program code;
- at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals;
- and
- a bus system;
- wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;
- the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system;
- and
- each of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system.
6 more elements
A computer system including:
- a plurality of data processing elements each including an arithmetic-logic unit;
- a plurality of memory elements adapted for storing at least one of program data and program code;
- at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals;
- and
- a bus system;
- wherein each of the data processing, memory, and input/output elements is separate from the others of the data processing, memory and input/output elements, and each of the data processing, memory, and input/output elements is adapted specifically to perform respectively the functions of data processing, memory storage, and input/output;
- and
- the bus system interconnects the data processing, memory, and input/output elements such that specific pairs of the elements are interconnected depending upon a setting of the bus system.
5 more elements
Dependencies are inferred from the claim text.