Dynamic high speed buffer with wide input noise margin

A circuit comprising:

• a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal, the first buffer exhibiting a first dynamic hysteresis range with a dynamic lower threshold and a dynamic upper threshold, the first buffer being configured to transition from a first hysteresis state in which the dynamic lower threshold has a first lower value and the dynamic upper threshold has a first upper value, to a second hysteresis state in which the dynamic lower threshold has a second lower value and the dynamic upper threshold has a second upper value;
• and
• a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting a second hysteresis range with a lower threshold and an upper threshold;
• and
• wherein
• the second buffer is configured to change a logic state of the second output signal when the incoming signal crosses the lower threshold or the upper threshold of the second hysteresis;
• the first buffer is configured to transition from the first hysteresis state to the second hysteresis state or from the second hysteresis state to the first hysteresis state in response to the logic state of the second output signal;
• and
• the first buffer is configured to change a logic state of the first output signal when the incoming signal crosses the dynamic lower threshold or the dynamic upper threshold of the first hysteresis.

A circuit comprising:

• a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal, the first buffer exhibiting a first dynamic hysteresis range with a dynamic lower threshold and a dynamic upper threshold, the first buffer being configured to transition from a first hysteresis state in which the dynamic lower threshold has a first lower value and the dynamic upper threshold has a first upper value, to a second hysteresis state in which the dynamic lower threshold has a second lower value and the dynamic upper threshold has a second upper value;
• and
• a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting a second hysteresis range with a lower threshold and an upper threshold;
• and
• wherein
• from a state in which the incoming signal is low, the first output signal is in a first logic state, the second output signal is in a second logic state, and the first buffer is in the first hysteresis state:
• when the incoming signal rises above the dynamic upper threshold of the first buffer, the first buffer transitions the first output signal to a third logic state;
• and
• when the incoming signal rises above the upper threshold of the second buffer, the second buffer transitions the second output signal to a fourth logic state, and the first buffer transitions from the first hysteresis state to the second hysteresis state based on the fourth logic state;
• and
• from a state in which the incoming signal is high, the first output signal is in the third logic state, the second output signal is in the fourth logic state, and the first buffer is in the second hysteresis state:
• when the incoming signal falls below the dynamic lower threshold of the first buffer, the first buffer transitions the first output signal to the first logic state;
• and
• when the incoming signal falls below the lower threshold of the second buffer, the second buffer transitions the second output signal to the second logic state, and the first buffer transitions from the second hysteresis state to the first hysteresis state based on the second logic state.