Apparatus and methods for a tamper resistant bus for secure lock bit transfer

In an integrated circuit, a tamper-resistant bus architecture for secure lock bit transfer, comprising:

• a nonvolatile memory having an n-bit storage region for storing encoded lock bits;
• a plurality of read access circuits coupled to the nonvolatile memory;
• an n-bit tamper-resistant bus coupled to the read access circuits;
• a decoder coupled to the tamper-resistant bus;
• a k-bit decoded lock signal bus coupled to the decoder;
• a controller coupled to the k-bit decoded lock signal bus;
• an encode control bus coupling encode control signals from the controller to the decoder;
• encode control circuitry disposed in the decoder and coupled to the encode control bus, the encode control circuitry having an output coupled to additional 1-bit lines of the tamper-resistant bus;
• and
• encode control circuitry disposed in the read access circuits and coupled to additional 1-bit lines of the tamper-resistant bus, the encode control circuitry encoding the lock bits read by the read access circuits before placing them on the tamper-resistant bus.