US 8,803,334 B2 · Semiconductor package including a semiconductor chip with a through silicon via

Abstract

A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

Claims20

Dependent claims

A semiconductor package, comprising:

a substrate;
a chip stack portion having a parallelepiped structure being disposed on the substrate and comprising a plurality of first semiconductor chips, the plurality first semiconductor chips comprising:
a first chip of the plurality of first semiconductor chips that includes a through silicon via (TSV), and
a second chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV;
an internal sealing member within the chip stack portion to fill a space between the first chip and the second chip;
at least one second semiconductor chip disposed on the chip stack portion;
and
a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other without using the TSV,
wherein an area of the at least one second semiconductor chip is smaller than an area of an upper area of the chip stack portion.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor package including a semiconductor chip with a through silicon via

Life of this patent

Semiconductor package including a semiconductor chip with a through silicon via

Life of this patent

Abstract

Claims20