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US 8,803,333 B2Granted
Three-dimensional chip stack and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Da-Yuan Shih, Chih-Hang Tung
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Abstract
A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.
Claims20
A device, comprising:
- a first chip comprising a first substrate and a first bump structure overlying the first substrate;
- and
- a second chip comprising a second substrate and a second bump structure overlying the second substrate, the first chip being bonded to the second chip by a solderless joint between the first bump structure and the second bump structure, the solderless joint having a joining region between the first bump structure and the second bump structure,
- wherein the joining region between the first chip and the second chip comprises a noble metal, the first bump structure comprises a metallization layer overlying the first substrate and a protection layer formed between the ioining region and the metallization layer, and a region between the first and the second chip is free from an adhesive material.
1 more element
A device, comprising:
- a first chip comprising a first semiconductor substrate, a first metal pillar overlying the first semiconductor substrate, a first protection layer overlying the first metal pillar, and a first bonding layer overlying the first protection layer;
- and
- a second chip comprising a second semiconductor substrate, a second metal pillar overlying the second semiconductor substrate, a second protection layer overlying the second metal pillar, and a second bonding layer overlying the second protection layer the first chip being bonded to the second chip by the first bonding layer and the second bonding layer, the first bonding layer and the second bonding layer forming a solderless joint between the first metal pillar and the second metal pillar,
- wherein the solderless joint has a joining region between the first chip and the second chip that comprises a noble metal, and a region between the first and the second chip is free from an adhesive material.
1 more element
A device, comprising:
- a first chip bonded to a second chip, the first chip comprising:
- a first metallization layer overlying a first passivation layer,
- a first protection layer overlying the first metallization layer, and
- a first bonding layer overlying the first protection layer;
- the second chip comprising:
- a second metallization layer overlying a second passivation layer;
- a second protection layer overlying the second metallization layer;
- and
- a second bonding layer overlying the second protection layer;
- wherein the first chip is bonded to the second chip by the first bonding layer and the second bonding layer, the first bonding layer and the second bonding layer forming a solderless joint having a joining region between the first chip and the second chip, the joining region comprises a noble metal, a region between the first and the second chip is free from an adhesive material, and has a thickness greater than or equal to 0.5 μm;
- and
- wherein the height between the first passivation layer and the second passivation layer is less than or equal to about 5 μm.
9 more elements
Dependencies are inferred from the claim text.