Stacked semiconductor package
AssigneeSK hynix Inc.
InventorSeong Cheol Kim
Life of this patent
Estimating the term…
Abstract
A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips.
Claims17
A stacked semiconductor package comprising:
- a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another;
- and
- interconnections electrically connecting the repair pads of the semiconductor chips;
- and
- conductive connection members formed between the through-silicon vias of the stacked semiconductor chips;
- and
- adhesive members formed between the stacked semiconductor chips.
Dependencies are inferred from the claim text.