Structures for improving current carrying capability of interconnects and methods of fabricating the same

A structure comprising:

• an under bump metallurgy in a trench, the under bump metallurgy including:
• an adhesion layer on a polyimide layer;
• a sputtered copper layer on the adhesion layer, the sputtered copper layer comprising a via depression located within the trench;
• a first plated nickel layer on the sputtered copper layer, the first plated nickel layer comprising a via depression located within the trench;
• a first plated copper layer on the first plated nickel layer, the first plated copper layer having a planar surface thereby eliminating via depressions, and the first plated copper layer completely filling the via depression of the first plated nickel layer;
• and
• a second plated nickel layer on the first plated copper layer, the second plated nickel layer having a planar surface thereby eliminating via depressions;
• and
• a reflowed solder bump on the under bump metallurgy.

A design structure embodied in a machine readable device or memory for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an under bump metallurgy formed in a trench, the under bump metallurgy including at least:
• an adhesion layer;
• a sputtered copper layer formed on the adhesion layer;
• a first plated nickel layer formed on the sputtered copper layer;
• a plated barrier layer that is a second plated nickel layer;
• and
• a plated conductive metal layer that is a first plated copper layer provided between the first plated nickel layer and the plated barrier layer;
• and
• a solder bump formed on the under bump metallurgy,
• wherein the first plated copper layer comprises a top surface that is entirely planar;
• the second plated nickel layer comprises a top surface that is entirely planar;
• the first plated nickel layer comprises a via depression located within the trench;
• and
• the sputtered copper layer comprises a via depression located within the trench.