Hybrid package construction with wire bond and through silicon vias
AssigneeQUALCOMM Incorporated
InventorsRatibor Radojcic, Arvind Chandrasekaran, Ryan Lane
Life of this patent
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AssigneeQUALCOMM Incorporated
InventorsRatibor Radojcic, Arvind Chandrasekaran, Ryan Lane
Estimating the term…
A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.
A semiconductor system, comprising:
A packaged semiconductor system, comprising:
A method of providing power to a stacked IC semiconductor system having a first tier die with a redistribution layer, an active side including active circuitry and a plurality of through silicon vias extending entirely through the first tier die and coupled to the redistribution layer, the first tier die mounted on a packaging substrate, and the semiconductor system further including a second tier die mounted on the first tier die, the second tier die being adjacent to the redistribution layer, the method comprising:
A semiconductor system, comprising:
A packaged semiconductor system, comprising:
Dependencies are inferred from the claim text.