Semiconductor package

A semiconductor package comprising:

• a substrate;
• at least a first semiconductor chip disposed on the substrate;
• at least a first terminal disposed on the substrate, the first terminal being electrically connected to the semiconductor chip and to an external source;
• a second terminal disposed on the substrate, the second terminal being electrically connected to the semiconductor chip and to a ground;
• a first sealant surrounding at least a portion of the semiconductor chip, the first sealant comprising a voltage sensitive material;
• a static electricity blocking layer disposed between the first sealant and the second terminal and between the first sealant and the first terminal, the static electricity blocking layer configured to prevent a conductive pathway from the first sealant to the first terminal;
• and
• a static electricity inducer including a conductive material, the static electricity inducer disposed to contact the first sealant and to be electrically connected to the second terminal.

A semiconductor package comprising:

• a substrate;
• at least a first semiconductor chip disposed on the substrate;
• at least a first communication terminal disposed on the substrate, the first communication terminal being electrically connected to the first semiconductor chip and to an external source;
• at least a first inducing terminal disposed on the substrate, the first inducing terminal being electrically connected to the semiconductor chip and to a ground;
• at least a first space filled with a non-conductive material and disposed to cover at least an active side of the first semiconductor chip and to surround at least one signal transmitting unit, wherein the signal transmitting unit is configured to electrically connect the first semiconductor chip to the first communication terminal;
• a static electricity inducer including a conductive material, the static electricity inducer disposed to surround the first space and to be electrically connected to the first inducing terminal;
• and
• a static electricity blocking layer disposed between the static electricity inducer and the first inducing terminal and between the static electricity inducer and the first communication terminal, the static electricity blocking layer configured to prevent a conductive pathway from being formed between the static electricity inducer and the first communication terminal.